Model-based simulation for SMT cores

Studies that evaluate new architectural designs of virtual memory typically employ a "model-based" methodology that relies on simulations of the translation lookaside buffer (TLB) coupled with empirical performance models. We observe that this methodology is limited in that each simulated thread of execution has its own dedicated TLB, whereas modern processors share a single TLB among multiple threads through simultaneous multithreading (SMT). Existing model-based research is thus unable to explore virtual memory designs in SMT context. We address this problem by developing a simulator that realistically combines memory reference streams of multiple SMT threads into one TLB. Our simulator is 99% accurate across four Intel processor generations running a wide range of memory-intensive workloads. Our validation efforts lead us to discover a previously undocumented eviction policy in Broadwell TLBs.