Michel Barreteau
- {1} "Placement Rapide Optimisé sur Machines Parallèles pour applications Télécoms", Project supported by the French Ministries of Industry and Research through the RNRT'98 (Réseau National de Recherche en Télécommunications) program, http://www.tcc.thomson-csf.com/promptGoogle Scholar
- {2} D. Maufroid, P. S. Paolucci, P. Kajfasz, A. Bertini, "mAgic FPU: VLIW Floating Point Engines for System-On-Chip Applications". Proc. EMMSEC'99, Stockholm, Sweden, (June, 1999).Google Scholar
- {3} http://ptolemy.eecs.berkeley.edu/Google Scholar
- {4} http://www-rocq.inria.fr/syndex/Google Scholar
- {5} http://www.gedae.comGoogle Scholar
- {6} T. Grandpierre, C. Lavarenne, Y. Sorel, "Optimized Rapid Prototyping for Real Time Embedded Heterogeneous Multi-Processors", CODES'99 : 7th International Workshop on Hardware/Software Co-Design, Rome, Italia (May, 1999). Google ScholarDigital Library
- {7} Y. Sorel, "Massively parallel systems with real-time constraints, the Algorithm Architecture Adequation Methodology", Proc. Massively Parallel Computing Systems, Italy (May, 1994).Google Scholar
- {8} C. Ancourt, D. Barthou, C. Guettier, F. Irigoin, B. Jeannet, J. Jourdan, J. Mattioli, "Automatic Data Mapping of Signal Processing Applications", IEEE International Conference on Application Specific Systems, Architectures and Processors, p. 350-362, Zurich, Switzerland (July, 1997). Google ScholarDigital Library
- {9} C. Guettier, "Optimisation globale du placement d'applications de traitement du signal sur architectures parallèles utilisant la programmation logique avec contraintes", PhD Thesis, Ecole des Mines de Paris, (December, 1997).Google Scholar
- {10} A. Demeure, A. Lafage, E. Boutillon, D. Rozzonelli, J-C. Dufourd, J-L. Marro, "Array-OL : proposition d'un formalisme Tableau pour le Traitement de Signal multi-dimensionnel", GRETSI'95, Juan-les-Pins, (France).Google Scholar
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