It is our great pleasure to welcome you to the 4th ACM/IEEE Workshop on Machine Learning for CAD (MLCAD 2022), held in-person in beautiful Snowbird, Utah! The MLCAD workshop focuses on Machine Learning (ML) methods for all aspects of CAD and electronic system design. The precursor for this workshop series was held at DATE-2019, and the inaugural workshop was in Banff in September 2019. Virtual workshops were held in 2020 and 2021.
Advances in ML over the past half-dozen years have revolutionized the effectiveness of ML for a variety of applications. However, design processes present challenges that require parallel advances in ML and CAD as compared to traditional ML applications. As such, the purpose of the MLCAD workshop is to discuss, define and provide a roadmap for the special needs for ML for CAD, where CAD is broadly defined to include both design-time techniques as well as run-time techniques.
MLCAD 2022 features contributions from industry, including tool vendors, as well as from academia, touching all aspects of CAD (from physical design to functional verifications) and from all over the world. This year's program includes 23 accepted papers, along with keynote talks from Ruchir Puri of IBM Research and Sankar Basu of the U.S. National Science Foundation. The program also includes six plenary and invited talks, and one panel. The accepted papers have undergone a rigorous review by an expert Technical Program Committee of 32 experts.
Proceeding Downloads
Placement Optimization via PPA-Directed Graph Clustering
In this paper, we present the first Power, Performance, and Area (PPA)-directed, end-to-end placement optimization framework that provides cell clustering constraints as placement guidance to advance commercial placers. Specifically, we formulate PPA ...
From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing Prediction
Timing prediction and optimization are challenging in design stages prior to detailed routing (DR) due to the unavailability of routing information. Inaccurate timing prediction wastes design effort, hurts circuit performance, and may lead to design ...
Faster FPGA Routing by Forecasting and Pre-Loading Congestion Information
Field Programmable Gate Array (FPGA) routing is one of the most time consuming tasks within the FPGA design flow, requiring hours and even days to complete for some large industrial designs. This is becoming a major concern for FPGA users and tool ...
Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards
There is still a great reliance on human expert knowledge during the analog integrated circuit sizing design phase due to its complexity and scale, with the result that there is a very low level of automation associated with it. Current research shows ...
LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces
A large body of literature has proved that the Bayesian optimization framework is especially efficient and effective in analog circuit synthesis. However, most of the previous research works only focus on designing informative surrogate models or ...
RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL
Analog/mixed-signal circuit design is one of the most complex and time-consuming stages in the whole chip design process. Due to various process, voltage, and temperature (PVT) variations from chip manufacturing, analog circuits inevitably suffer from ...
Automatic Analog Schematic Diagram Generation based on Building Block Classification and Reinforcement Learning
Schematic visualization is important for analog circuit designers to quickly recognize the structures and functions of transistor-level circuit netlists. However, most of the original analog design or other automatically extracted analog circuits are ...
The Changing Landscape of AI-driven System Optimization for Complex Combinatorial Optimization
With the unprecedented success of modern machine learning in areas like computer vision and natural language processing, a natural question is where can it have maximum impact in real life. At Intel Labs, we are actively investing in research that ...
AI Chips Built by AI - Promise or Reality?: An Industry Perspective
Artificial Intelligence is an avenue to innovation that is touching every industry worldwide. AI has made rapid advances in areas like speech and image recognition, gaming, and even self-driving cars, essentially automating less complex human tasks. In ...
ML for Analog Design: Good Progress, but More to Do
Analog and mixed-signal (AMS) blocks are often critical and time-consuming part of System-on-Chip (SoC) design, due to the largely manual process of circuit design, simulation and SoC integration iterations. There have been numerous efforts to realize ...
SpeedER: A Supervised Encoder-Decoder Driven Engine for Effective Resistance Estimation of Power Delivery Networks
Voltage (IR) analysis tools need to be launched multiple times during the Engineering Change Order (ECO) phase in the modern design cycle for Power Delivery Network (PDN) refinement, while analyzing the IR characteristics of advanced chip designs by ...
XT-PRAGGMA: Crosstalk Pessimism Reduction Achieved with GPU Gate-level Simulations and Machine Learning
- Vidya A. Chhabria,
- Ben Keller,
- Yanqing Zhang,
- Sandeep Vollala,
- Sreedhar Pratty,
- Haoxing Ren,
- Brucek Khailany
Accurate crosstalk-aware timing analysis is critical in nanometer-scale process nodes. While today's VLSI flows rely on static timing analysis (STA) techniques to perform crosstalk-aware timing signoff, these techniques are limited due to their static ...
Fast Prediction of Dynamic IR-Drop Using Recurrent U-Net Architecture
Recurrent U-Net (RU-Net) is employed for fast prediction of dynamic IR-drop when power distribution network (PDN) contains capacitor components. Each capacitor can be modeled by a resistor and a current source, which is a function of v(t-Δ t) node ...
Efficient Design Rule Checking Script Generation via Key Information Extraction
Design rule checking (DRC) is a critical step in integrated circuit design. DRC requires formatted scripts as the input to the design rule checker. However, these scripts are always generated manually in the foundry, and such a generation process is ...
Scan Chain Clustering and Optimization with Constrained Clustering and Reinforcement Learning
Scan chains are used in design for test by providing controllability and observability at each register. Scan optimization is run during physical design after placement where scannable elements are re-ordered along the chain to reduce total wirelength (...
Autoencoder-Based Data Sampling for Machine Learning-Based Lithography Hotspot Detection
Technology scaling has increased the complexity of integrated circuit design. It has also led to more challenges in the field of Design for Manufacturing (DFM). One of these challenges is lithography hotspot detection. Hotspots (HS) are design patterns ...
Driving Early Physical Synthesis Exploration through End-of-Flow Total Power Prediction
Leading-edge designs on advanced nodes are pushing physical design (PD) flow runtime into several weeks. Stringent time-to-market constraint necessitates efficient power, performance, and area (PPA) exploration by developing accurate models to evaluate ...
Towards Neural Hardware Search: Power Estimation of CNNs for GPGPUs with Dynamic Frequency Scaling
Machine Learning (ML) algorithms are essential for emerging technologies such as autonomous driving and application-specific Internet of Things(IoT) devices. Convolutional Neural Network(CNN) is one of the major techniques used in such systems. This ...
A Thermal Machine Learning Solver For Chip Simulation
Thermal analysis provides deeper insights into electronic chips' behavior under different temperature scenarios and enables faster design exploration. However, obtaining detailed and accurate thermal profile on chip is very time-consuming using FEM or ...
Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms
- Hadi Esmaeilzadeh,
- Soroush Ghodrati,
- Andrew B. Kahng,
- Joon Kyung Kim,
- Sean Kinzer,
- Sayak Kundu,
- Rohan Mahapatra,
- Susmita Dey Manasi,
- Sachin S. Sapatnekar,
- Zhiang Wang,
- Ziqing Zeng
Parameterizable ML accelerators are the product of recent breakthroughs in machine learning (ML). To fully enable the design space exploration, we propose a physical-design-driven, learning-based prediction framework for hardware-accelerated deep neural ...
Graph Representation Learning for Gate Arrival Time Prediction
An accurate estimate of the timing profile at different stages of the physical design flow allows for pre-emptive changes to the circuit, significantly reducing the design time and effort. In this work, a graph based deep regression model is utilized to ...
A Tale of EDA's Long Tail: Long-Tailed Distribution Learning for Electronic Design Automation
Long-tailed distribution is a common and critical issue in the field of machine learning. While prior work addressed data imbalance in several tasks in electronic design automation (EDA), insufficient attention has been paid to the long-tailed ...
Industrial Experience with Open-Source EDA Tools
Commonly, the design flow of integrated circuits from initial specifications to fabrication employs commercial, proprietary EDA tools. While these tools deliver high-quality, production-ready results, they can be seen as expensive black boxes and thus, ...
Invertible Neural Networks for Design of Broadband Active Mixers
In this work, we present the invertible neural network for predicting the posterior distributions of the design space of broadband active mixers with RF from 100 MHz to 10 GHz. This invertible method gives a fast and accurate model when investigating ...
High Dimensional Optimization for Electronic Design
Bayesian optimization (BO) samples points of interest to update a surrogate model for a blackbox function. This makes it a powerful technique to optimize electronic designs which have unknown objective functions and demand high computational cost of ...
Transfer of Performance Models Across Analog Circuit Topologies with Graph Neural Networks
In this work, graph neural networks (GNNs) and transfer learning are leveraged to transfer device sizing knowledge learned from data of related analog circuit topologies to predict the performance of a new topology. A graph is generated from the netlist ...
RxGAN: Modeling High-Speed Receiver through Generative Adversarial Networks
- Priyank Kashyap,
- Archit Gajjar,
- Yongjin Choi,
- Chau-Wai Wong,
- Dror Baron,
- Tianfu Wu,
- Chris Cheng,
- Paul Franzon
Creating models for modern high-speed receivers using circuit-level simulations is costly, as it requires computationally expensive simulations and upwards of months to finalize a model. Added to this is that many models do not necessarily agree with ...
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Acceptance Rates
Year | Submitted | Accepted | Rate |
---|---|---|---|
MLCAD '24 | 83 | 35 | 42% |
Overall | 83 | 35 | 42% |