Hung-Yun Hsu
ABSTRACT
Schematic visualization is important for analog circuit designers to quickly recognize the structures and functions of transistor-level circuit netlists. However, most of the original analog design or other automatically extracted analog circuits are stored in the form of transistor-level netlists in the SPICE format. It can be error-prone and time-consuming to manually create an elegant and readable schematic from a netlist. Different from the conventional graph-based methods, this paper introduces a novel analog schematic diagram generation flow based on comprehensive building block classification and reinforcement learning. The experimental results show that the proposed method can effectively generate aesthetic analog circuit schematics with a higher building block compliance rate, and fewer numbers of wire bends and net crossings, resulting in better readability, compared with existing methods and modern tools.
- G. Swinkels and L. Hafer, "Schematic generation with an expert system," IEEE TCAD, vol. 9, no. 12, pp. 1289--1306, 1990.Google Scholar
- Y.-S. Jehng, L.-G. Chen, and T.-M. Parng, "ASG: Automatic schematic generator," Integration, vol. 11, no. 1, pp. 11--27, 1991.Google ScholarDigital Library
- T.-C. Chiueh, "HERESY: a hybrid approach to automatic schematic generation for VLSI," in Proc. DATE, 1991, pp. 419--423.Google Scholar
- S. Frezza and S. Levitan, "SPAR: a schematic place and route system," IEEE TCAD, vol. 12, no. 7, pp. 956--973, 1993.Google Scholar
- B. Naveen and K. Raghunathan, "An automatic netlist-to-schematic generator," IEEE Design & Test of Computers, vol. 10, no. 1, pp. 36--41, 1993.Google ScholarDigital Library
- N.-H. Kim, K.-S. Kim, K.-M. Choi, and J.-T. Kong, "RightTopologizer: an efficient schematic generator for multi-level optimization," in Proc. SOCC, 2000, pp. 387--391.Google Scholar
- P.-H. Lin and S.-C. Lin, "Schematic diagram generation and display system," U.S. Patent 7,178,123, 2007.Google Scholar
- B. Arsintescu, "A method for analog circuits visualization," in Proc. ICCD, 1996, pp. 454--459.Google Scholar
- Lee and McNamee, "Aesthetic routing for transistor schematics," in Proc. ICCAD, 1992, pp. 35--38.Google Scholar
- T.-H. Tsai, P.-H. Lin, S.-C. Lin, and H.-C. Yu, "Rule-based schematic diagram generator," U.S. Patent 7,386,823, 2008.Google Scholar
- B. Singh, D. Oriordan, B. G. Arsintescu, A. Goel, and D. R. Deshpande, "System and method for circuit schematic generation," U.S. Patent 7,917,877, 2011.Google Scholar
- B. Garg, R. Sehgal, and A. Singh, "Schematic generation visualization aid for netlists comprising analog circuits," U.S. Patent 8,504,953, 2013.Google Scholar
- T. Massier, H. Graeb, and U. Schlichtmann, "The sizing rules method for cmos and bipolar analog integrated circuit synthesis," IEEE TCAD, vol. 27, no. 12, pp. 2209--2222, 2008.Google Scholar
- M. Eick, M. Strasser, H. E. Graeb, and U. Schlichtmann, "Automatic generation of hierarchical placement rules for analog integrated circuits," in Proc. ISPD, 2010, pp. 47--54.Google Scholar
- M. Eick, M. Strasser, K. Lu, U. Schlichtmann, and H. E. Graeb, "Comprehensive generation of hierarchical placement rules for analog integrated circuits," IEEE TCAD, vol. 30, no. 2, pp. 180--193, 2011.Google Scholar
- M. P.-H. Lin, H.-Y. Chi, A. Patyal, Z.-Y. Liu, J.-J. Zhao, C.-N. J. Liu, and H.-M. Chen, "Achieving analog layout integrity through learning and migration invited talk," in Proc. ICCAD, 2020, pp. 1--8.Google Scholar
- J. Schulman, F. Wolski, P. Dhariwal, A. Radford, and O. Klimov, "Proximal policy optimization algorithms," arXiv preprint arXiv:1707.06347, 2017.Google Scholar
- J. Rosa, D. Guerra, N. Horta, R. Martins, and N. Lourencc o, Using Artificial Neural Networks for Analog Integrated Circuit Design Automation, ser. Springer Briefs in Applied Sciences and Technology. Springer International Publishing, 2019.Google Scholar
- H. Wang, K. Wang, J. Yang, L. Shen, N. Sun, H.-S. Lee, and S. Han, "GCN-RL circuit designer: Transferable transistor sizing with graph neural networks and reinforcement learning," in Proc. DAC, 2020, pp. 1--6.Google ScholarCross Ref
- M. Eick and H. E. Graeb, "MARS: Matching-driven analog sizing," IEEE TCAD, vol. 31, no. 8, pp. 1145--1158, 2012.Google Scholar
- A. Patyal, H.-M. Chen, M. P.-H. Lin, G.-Q. Fang, and S. Y.-H. Chen, "Pole-aware analog layout synthesis considering monotonic current flows and wire-crossings," IEEE TCAD, 2022.Google Scholar
Index Terms
- Automatic Analog Schematic Diagram Generation based on Building Block Classification and Reinforcement Learning
Recommendations
RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL
MLCAD '22: Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CADAnalog/mixed-signal circuit design is one of the most complex and time-consuming stages in the whole chip design process. Due to various process, voltage, and temperature (PVT) variations from chip manufacturing, analog circuits inevitably suffer from ...
Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits
GLSVLSI '20: Proceedings of the 2020 on Great Lakes Symposium on VLSIThe superconducting rapid single flux quantum (RSFQ) logic circuit has the characteristics of high speed and low power consumption, making it an attractive candidate for future supercomputers. However, computer-aided design (CAD) tools for CMOS cannot ...
Controllable decoding for automated analog circuit structure design
The decoding scheme is a major problem in automated analog circuit topology synthesis since decoding schemes bias synthesized circuit structures. However, the proper decoding scheme varies depending on the method to realize a given function. In this ...
Comments