Naiju Karim Abdul
ABSTRACT
Scan chains are used in design for test by providing controllability and observability at each register. Scan optimization is run during physical design after placement where scannable elements are re-ordered along the chain to reduce total wirelength (and power). In this paper, we present a machine learning based technique that leverages constrained clustering and reinforcement learning to obtain a wirelength efficient scan chain solution. Novel techniques like next-min sorted assignment, clustered assignment, node collapsing, partitioned Q-Learning and in-context start-end node determination are introduced to enable improved wire length while honoring design-for-test constraints. The proposed method is shown to provide up to 24% scan wirelength reduction over a traditional algorithmic optimization technique across 188 moderately sized blocks from an industrial 7nm design.
Supplemental Material
- Benavent, E., Martínez, "A. Multi-depot Multiple TSP: a polyhedral study and computational results", Ann Oper Res 207, 7--25 (2013). https://doi.org/10.1007/s10479-011--1024-yGoogle Scholar
Cross Ref
- Jiann-Chyi Rau, Ching-Hsiu Lin and Jun-Yi Chang, "An efficient low-overhead policy for constructing multiple scan-chains", 13th Asian Test Symposium, 2004, pp. 82--87, doi: 10.1109/ATS.2004.23.Google ScholarDigital Library
- S. Kobayashi, M. Edahiro and M. Kubo, "Scan-chain optimization algorithms for multiple scan-paths", Proceedings of 1998 ASPDAC, pp. 301--306, doi: 10.1109/ASPDAC.1998.669474.Google Scholar
- D. Berthelot, S. Chaudhuri and H. Savoj, "An efficient linear time algorithm for scan chain optimization and repartitioning", Proceedings. International Test Conference, 2002, pp. 781--787, doi: 10.1109/TEST.2002.1041831.Google ScholarCross Ref
- B. B. Paul, R. Mukhopadhyay and I. S. Gupta, "Genetic Algorithm based Scan Chain Optimization and Test Power Reduction using Physical Information", TENCON 2006 - 2006 IEEE Region 10 Conference, 2006, pp. 1--4, doi: 10.1109/TENCON.2006.344008.Google ScholarCross Ref
- Li-Chung Hsu and Hung-Ming Chen, "On optimizing scan testing power and routing cost in scan chain design", 7th ISQED 2006, pp. 6 pp.-456, doi: 10.1109/ISQED.2006.95.Google ScholarDigital Library
- H. Dai, E.B. Khalil, Y.Zhang, C, Dilking, Le Song, "Learning Combinatorial Optimization Algorithms over Graphs", NIPS 2017, arXiv:1704.01665Google Scholar
- L.M. Gambardella , M.Dorigo, "Ant-Q: A Reinforcement Learning approach to the traveling salesman problem", ML-95, Twelfth International Conf. on Machine Learning, 1995Google Scholar
- A. D. Tijsma, M. M. Drugan and M. A. Wiering, "Comparing exploration strategies for Q-learning in random stochastic mazes", 2016 IEEE SSCI, 2016, pp. 1--8, doi: 10.1109/SSCI.2016.7849366.Google Scholar
- Sutton, R. S. & Barto, A. G. (2018 ), "Reinforcement Learning: An Introduction", The MIT PressGoogle Scholar
- R. M. Rao et al., "POWER10": A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology", 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 48--50, doi: 10.1109/ISSCC42614.2022.9731594Google ScholarCross Ref
Index Terms
- Scan Chain Clustering and Optimization with Constrained Clustering and Reinforcement Learning
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