Yajuan Du
ABSTRACT
3D flash memory is becoming the mainstream of Solid-State Drives (SSDs) because of its large storage capacity achieved by vertically stacking planar flash into multiple layers. This special vertical structure introduces two additional error sources: the intra-wordline error variation between upper pages and lower pages inside the same wordlines, and the inter-layer error variation across different layers inside one flash block. Recent works have studied polar code in flash memory, which is the first Error Checking and Correcting (ECC) that is proven to reach the Shannon's channel capacity. However, due to the special error characteristic mentioned above, polar codes cannot display effective error correction capabilities in 3D flash.
This paper initially analyzes the challenges of polar codes and proposes an effective polar code design for 3D flash memories, named as Error Variation Aware Polar Code (EvaPC). By exploiting layer-induced error variations and characteristics of polar code encoding/decoding, we implement two schemes: intra-wordline error aware data placement and layer-adaptive polar code. The former places important bits of codewords into lower pages with lower error rates, while the latter applies varied polar code rates across different layers to improve space efficiency by providing equivalent ECC capability. A series of experimental results show that EvaPC can enable polar codes on 3D flash memories with efficient error correction capability and space utilization efficiency.
- E. Arikan. 2009. Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels. IEEE Transactions on Information Theory 55, 7 (2009), 3051--3073.Google Scholar
Digital Library
- Shuo Han Chen, Yen Ting Chen, Hsin Wen Wei, and Wei Kuan Shih. 2017. Boosting the Performance of 3D Charge Trap NAND Flash with Asymmetric Feature Process Size Characteristic. In DAC. 83.Google Scholar
- Sae-Young Chung, Thomas J. Richardson, and Rüdiger L. Urbanke. 2001. Analysis of sum-product decoding of low-density parity-check codes using a Gaussian approximation. IEEE Trans. Information Theory 47, 2 (2001), 657--670.Google ScholarDigital Library
- Luca Crippa and Rino Micheloni. 2016. 3D Charge Trap NAND Flash Memories. In 3D Flash Memories. 85--127. Google ScholarCross Ref
- Chong Leong Gan and Uda Hashim. 2016. 3D Flash Memories. Microelectronics Reliability 65 (2016), 327--328. Google ScholarCross Ref
- Congming Gao, Min Ye, Qiao Li, Chun Jason Xue, Youtao Zhang, Liang Shi, and Jun Yang. 2019. Constructing Large, Durable and Fast SSD System via Reprogramming 3D TLC Flash Memory. In MICRO. 493--505.Google Scholar
- K. Hsu, C. Tsao, Y. Chang, T. W. Kuo, and Y. Huang. 2018. Proactive channel adjustment to improve polar code capability for flash storage devices. IEEE.Google Scholar
- N. Hussami, S. B. Korada, and R. Urbanke. 2009. Performance of Polar Codes for Channel and Source Coding. IEEE.Google Scholar
- Dongku Kang, Minsu Kim, Su Chang Jeon, Wontaeck Jung, Jooyong Park, Gyosoo Choo, et al. 2019. A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface. In ISSCC. 216--218. Google ScholarCross Ref
- Chulbum Kim, Doo-Hyun Kim, Woopyo Jeong, Hyun-Jin Kim, Il Han Park, Hyun-Wook Park, JongHoon Lee, JiYoon Park, Yang-Lo Ahn, Ji Young Lee, et al. 2018. A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory. IEEE Journal of Solid-State Circuits 53, 1 (2018), 124--133.Google ScholarCross Ref
- S. Lee, C. Kim, and M. Kim et al. 2018. A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput. In ISSCC. 340--342. Google ScholarCross Ref
- Qing Li, Anxiao Jiang, and Erich F. Haratsch. 2014. Noise modeling and capacity analysis for NAND flash memories. In 2014 IEEE International Symposium on Information Theory, Honolulu, HI, USA, June 29 - July 4, 2014. 2262--2266.Google ScholarCross Ref
- Yue Li, Hakim Alhussien, Erich F. Haratsch, and Anxiao Andrew Jiang. 2015. A study of polar codes for MLC NAND flash memories. In ICNC. 608--612.Google Scholar
- Weihua Liu, Fei Wu, Meng Zhang, Yifei Wang, Zhonghai Lu, Xiangfeng Lu, and Changsheng Xie. 2019. Characterizing the Reliability and Threshold Voltage Shifting of 3D Charge Trap NAND Flash. In DATE. 312--315. Google ScholarCross Ref
- Yixin Luo, Saugata Ghose, Yu Cai, Erich F Haratsch, and Onur Mutlu. 2018. Improving 3D NAND flash memory lifetime by tolerating early retention loss and process variation. In Abstracts of the 2018 ACM International Conference on Measurement and Modeling of Computer Systems. ACM, 106--106.Google ScholarDigital Library
- Rino Micheloni, Luca Crippa, Cristian Zambelli, and Piero Olivo. 2017. Architectural and Integration Options for 3D NAND Flash Memories. Computers 6, 3 (2017), 27. Google ScholarCross Ref
- N. Papandreou, H. Pozidis, T. Parnell, N. Ioannou, and T. Fisher. 2019. Characterization and Analysis of Bit Errors in 3D TLC NAND Flash Memory. In IRPS.Google Scholar
- Ido Tal and Alexander Vardy. 2012. List Decoding of Polar Codes. CoRR abs/1206.0050 (2012). arXiv:1206.0050 http://arxiv.org/abs/1206.0050Google Scholar
- Ido Tal and Alexander Vardy. 2013. How to Construct Polar Codes. IEEE Trans. Information Theory 59, 10 (2013), 6562--6582.Google ScholarDigital Library
- Toshiba. 2017. 3D Flash Memory: Scalable, High Density Storage for Large Capacity Applications. https://www.toshiba.com/tma/technologymoves/3d-flash.jsp. Accessed: 2018-11.Google Scholar
- P. Trifonov. 2012. Efficient Design and Decoding of Polar Codes. IEEE Transactions on Communications 60, 11 (2012), 3221--3227.Google ScholarCross Ref
- Fei Wu, Zuo Lu, You Zhou, Xubin He, Zhi-hu Tan, and Changsheng Xie. 2018. OSPADA: One-Shot Programming Aware Data Allocation Policy to Improve 3D NAND Flash Read Performance. In ICCD. 51--58.Google Scholar
- F. Wu, Y. Zhu, Q. Xiong, Z. Lu, Y. Zhou, W. Kong, and C. Xie. 2018. Characterizing 3D Charge Trap NAND Flash: Observations, Analyses and Applications. In ICCD. 381--388. Google ScholarCross Ref
- Yi Zhong, Chun Zhang, Chenrong Xiong, and Zhiyuan Yan. 2017. Multi-rate polar codes for solid state drives. In ICASSP. 1128--1132.Google Scholar
Index Terms
- Enhancing Polar Codes Efficiency on 3D Flash Memory by Exploiting Multiple Error Variations
Recommendations
Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics
3D flash memories have been widely developed to further increase the storage capacity of SSDs by vertically stacking multiple layers. However, this special physical structure brings new error characteristics. Existing studies have discovered that there ...
Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement
Considering 3D NAND flash has a new property of process variation (PV), which causes different raw bit error rates (RBER) among different layers of the flash block. This paper builds a mathematical model for estimating the retention errors of flash cells, ...
Adapting Layer RBERs Variations of 3D Flash Memories via Multi-granularity Progressive LDPC Reading
DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019Existing studies have uncovered that there exist significant Raw Bit Error Rates (RBERs) variations among different layers of 3D flash memories due to manufacture process variation. These RBER variations would cause significantly diversed read latencies ...
Comments