research-article

GraphPlanner: Floorplanning with Graph Neural Network

Authors:

Li ShangAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems, Volume 28, Issue 2

Article No.: 21, Pages 1 - 24

https://doi.org/10.1145/3555804

Published: 24 December 2022 Publication History

Abstract

Chip floorplanning has long been a critical task with high computation complexity in the physical implementation of VLSI chips. Its key objective is to determine the initial locations of large chip modules with minimized wirelength while adhering to the density constraint, which in essence is a process of constructing an optimized mapping from circuit connectivity to physical locations. Proven to be an NP-hard problem, chip floorplanning is difficult to be solved efficiently using algorithmic approaches. This article presents GraphPlanner, a variational graph-convolutional-network-based deep learning technique for chip floorplanning. GraphPlanner is able to learn an optimized and generalized mapping between circuit connectivity and physical wirelength and produce a chip floorplan using efficient model inference. GraphPlanner is further equipped with an efficient clustering method, a unification of hyperedge coarsening with graph spectral clustering, to partition a large-scale netlist into high-quality clusters with minimized inter-cluster weighted connectivity. GraphPlanner has been integrated with two state-of-the-art mixed-size placers. Experimental studies using both academic benchmarks and industrial designs demonstrate that compared to state-of-the-art mixed-size placers alone, GraphPlanner improves placement runtime by 25% with 4% wirelength reduction on average.

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Cited By

Li ZTian KZhai JLi ZKai SXu SYu BZhao KNakamura YWang Y(2025)FTAFP: A Feedthrough-Aware Floorplanner for Hierarchical Design of Large-Scale SoCsProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3697728(886-892)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3697728
Kahng AWang Z(2025)DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning AcceleratorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.343652144:2(696-708)Online publication date: Feb-2025
https://doi.org/10.1109/TCAD.2024.3436521
H. K. YK. SBiyani SM. S. S(2024)Optimization of Analog Circuit Placement: A Graph Neural Network ApproachProceedings of the 2024 10th International Conference on Computing and Artificial Intelligence10.1145/3669754.3669815(399-403)Online publication date: 26-Apr-2024
https://dl.acm.org/doi/10.1145/3669754.3669815
Show More Cited By

Index Terms

GraphPlanner: Floorplanning with Graph Neural Network
1. Computer systems organization
  1. Architectures
2. Computing methodologies
  1. Machine learning
    1. Machine learning approaches
      1. Neural networks

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 28, Issue 2

March 2023

409 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3573314

Editor:
X. Sharon Hu
University of Notre Dame, USA

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 24 December 2022

Online AM: 17 August 2022

Accepted: 24 July 2022

Revised: 15 July 2022

Received: 15 February 2022

Published in TODAES Volume 28, Issue 2

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National Natural Science Foundation of China (NSFC)
National Key R&D Program of China
Young Scientist project of MOE

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Cited By

Li ZTian KZhai JLi ZKai SXu SYu BZhao KNakamura YWang Y(2025)FTAFP: A Feedthrough-Aware Floorplanner for Hierarchical Design of Large-Scale SoCsProceedings of the 30th Asia and South Pacific Design Automation Conference10.1145/3658617.3697728(886-892)Online publication date: 20-Jan-2025
https://dl.acm.org/doi/10.1145/3658617.3697728
Kahng AWang Z(2025)DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning AcceleratorsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.343652144:2(696-708)Online publication date: Feb-2025
https://doi.org/10.1109/TCAD.2024.3436521
H. K. YK. SBiyani SM. S. S(2024)Optimization of Analog Circuit Placement: A Graph Neural Network ApproachProceedings of the 2024 10th International Conference on Computing and Artificial Intelligence10.1145/3669754.3669815(399-403)Online publication date: 26-Apr-2024
https://dl.acm.org/doi/10.1145/3669754.3669815
Dinh TDo T(2024)Graph-Based Ranking Techniques for Improving VLSI Placement2024 IEEE 15th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON)10.1109/UEMCON62879.2024.10754775(715-719)Online publication date: 17-Oct-2024
https://doi.org/10.1109/UEMCON62879.2024.10754775
Liu YZhou HWang JYang FZeng XShang L(2024)Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary ConditionsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2024.336366632:5(810-822)Online publication date: 8-Mar-2024
https://dl.acm.org/doi/10.1109/TVLSI.2024.3363666
Chen YWen ZLiang YLin Y(2023)Stronger Mixed-Size Placement Backbone Considering Second-Order Information2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323700(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323700

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