A Machine Learning Approach for Accelerating SimPL-Based Global Placement for FPGA's
Authors: 
Tianyi Yu, Nima Karimpour Darav, 
Ismail Bustany, Mehrdad Eslami DehkordiAuthors Info & Claims
Tianyi Yu, Nima Karimpour Darav, Ismail Bustany, Mehrdad Eslami DehkordiAuthors Info & ClaimsArticle No.: 5, Pages 1 - 7
Abstract
Many commercial FPGA placement tools are based on the SimPL framework where the Lower Bound (LB) phase optimizes wire length and timing without considering cell overlaps and the Upper Bound (UB) phase spreads out cells while considering the target FPGA architectures. In the SimPL framework, the number of iterations depends on design complexity and the quality of UB placement, which highly impacts runtime. In this work, we propose a machine learning (ML) scheme where the anchor weights of cells are dynamically adjusted to make the process converge in a pre-determined budget for the number of iterations. In our approach and for a given FPGA architecture, a ML model constructs a trajectory guide function that is used for adjusting anchor weights during SimPL's iterations. Our experimental results on industrial benchmarks show, we can achieve on average 28.01% and 4.7% runtime reduction in the runtime of Global Placement and the runtime of the whole placer, respectively while maintaining the quality of solutions within an acceptable range.
References
[1]
Vaughn Betz and Jonathan Rose. 1997. VPR: A New Packing, Placement and Routing Tool for FPGA Research. In Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications (FPL '97). Springer-Verlag, Berlin, Heidelberg, 213--222.
[2]
L. Breiman, J. H. Friedman, R. A. Olshen, and C. J. Stone. 1984. Classification and Regression Trees. Wadsworth and Brooks, Monterey, CA.
[3]
Nima Karimpour Darav, Andrew Kennings, Aysa Fakheri Tabrizi, David Westwick, and Laleh Behjat. 2016. Eh?Placer: A High-Performance Modern Technology-Driven Placer. ACM Trans. Des. Autom. Electron. Syst. 21, 3, Article 37 (apr 2016), 27 pages.
[4]
Marcel Gort and Jason H. Anderson. 2012. Analytical placement for heterogeneous FPGAs. In 22nd International Conference on Field Programmable Logic and Applications (FPL). 143--150.
[5]
Xu He, Tao Huang, Linfu Xiao, Haitong Tian, and Evangeline F. Y. Young. 2013. Ripple: A Robust and Effective Routability-Driven Placer. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, 10 (2013), 1546--1556.
[6]
Xilinx Inc. 2021. Vivado Design Suite User Guide. "https://www.xilinx.com/content/dam/xilinx/support/documents/sw_manuals/xilinx2021_2/ug910-vivado-getting-started.pdf"
[7]
Nima Karimpour Darav, Andrew Kennings, Kristofer Vorwerk, and Arun Kundu. 2019. Multi-Commodity Flow-Based Spreading in a Commercial Analytic Placer. In Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (Seaside, CA, USA) (FPGA '19). Association for Computing Machinery, New York, NY, USA, 122--131.
[8]
Guolin Ke, Qi Meng, Thomas Finley, Taifeng Wang, Wei Chen, Weidong Ma, Qiwei Ye, and Tie-Yan Liu. 2017. LightGBM: A Highly Efficient Gradient Boosting Decision Tree. In Advances in Neural Information Processing Systems, I. Guyon, U. Von Luxburg, S. Bengio, H. Wallach, R. Fergus, S. Vishwanathan, and R. Garnett (Eds.), Vol. 30. Curran Associates, Inc. https://proceedings.neurips.cc/paper/2017/file/6449f44a102fde848669bdd9eb6b76fa-Paper.pdf
[9]
Myung-Chul Kim, Dong-Jin Lee, and Igor L. Markov. 2012. SimPL: An Effective Placement Algorithm. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, 1 (2012), 50--60.
[10]
Wuxi Li, Shounak Dhar, and David Z. Pan. 2018. UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, 4 (2018), 869--882.
[11]
Wuxi Li, Yibo Lin, and David Z. Pan. 2019. elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs. In 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 1--8.
[12]
Tao Lin, Chris Chu, Joseph R. Shinnerl, Ismail Bustany, and Ivailo Nedelchev. 2015. POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, 3 (2015), 447--459.
[13]
Jingwei Lu, Hao Zhuang, Pengwen Chen, Hongliang Chang, Chin-Chih Chang, Yiu-Chung Wong, Lu Sha, Dennis Huang, Yufeng Luo, Chin-Chi Teng, and Chung-Kuan Cheng. 2015. ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, 5 (2015), 685--698.
[14]
P. Maidee, C. Ababei, and K. Bazargan. 2005. Timing-driven partitioning-based placement for island style FPGAs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, 3 (2005), 395--406.
[15]
Ryan Pattison, Ziad Abuowaimer, Shawki Areibi, Gary Gréwal, and Anthony Vannelli. 2016. GPlace: A congestion-aware placement tool for UltraScale FPGAs. In 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 1--7.
[16]
Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, and Bei Yu. 2016. RippleFPGA: A routability-driven placement for large-scale heterogeneous FPGAs. In 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 1--8.
[17]
Xilinx. 2022. Versal Architecture and Product Data Sheet: Overview. https://docs.xilinx.com/v/u/en-US/ds950-versal-overview
[18]
Stephen Yang, Aman Gayasen, Chandra Mulpuri, Sainath Reddy, and Rajat Aggarwal. 2016. Routability-Driven FPGA Placement Contest. In Proceedings of the 2016 on International Symposium on Physical Design (Santa Rosa, California, USA) (ISPD '16). Association for Computing Machinery, New York, NY, USA, 139--143.
[19]
Stephen Yang, Chandra Mulpuri, Sainath Reddy, Meghraj Kalase, Srinivasan Dasasathyan, Mehrdad E. Dehkordi, Marvin Tom, and Rajat Aggarwal. 2017. Clock-Aware FPGA Placement Contest. In Proceedings of the 2017 ACM on International Symposium on Physical Design (Portland, Oregon, USA) (ISPD '17). Association for Computing Machinery, New York, NY, USA, 159--164.
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Published: 27 January 2023
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