research-article

Performance-driven Wire Sizing for Analog Integrated Circuits

Authors:

Meghna Madhusudan,

Sachin Sapatnekar,

Ramesh Harjani,

Jiang HuAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems, Volume 28, Issue 2

Article No.: 19, Pages 1 - 23

https://doi.org/10.1145/3559542

Published: 24 December 2022 Publication History

Abstract

Analog IC performance has a strong dependence on interconnect RC parasitics, which are significantly affected by wire sizes in recent technologies, where minimum-width wires have high resistance. However, performance-driven wire sizing for analog ICs has received very little research attention. In order to fill this void, we develop several techniques to facilitate an end-to-end automatic wire sizing approach. They include a circuit performance model based on customized graph neural network (GNN) and two optimization techniques: one using Bayesian optimization accelerated by the GNN model, and the other based on TensorFlow training. Experimental results show that our technique can achieve 11% circuit performance improvement or 8.7× speedup compared to a conventional Bayesian optimization method.

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Cited By

Zhou HLi YXiong XZhou P(2024)A Transferable GNN-based Multi-Corner Performance Variability Modeling for Analog ICs2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473858(411-416)Online publication date: 22-Jan-2024
https://doi.org/10.1109/ASP-DAC58780.2024.10473858

Index Terms

Performance-driven Wire Sizing for Analog Integrated Circuits
1. Hardware
  1. Electronic design automation
    1. Methodologies for EDA
      1. Software tools for EDA
    2. Physical design (EDA)
      1. Wire routing
  2. Very large scale integration design
    1. Analog and mixed-signal circuits
      1. Analog and mixed-signal circuit optimization

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 28, Issue 2

March 2023

409 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3573314

Editor:
X. Sharon Hu
University of Notre Dame, USA

Issue’s Table of Contents

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 24 December 2022

Online AM: 26 August 2022

Accepted: 19 August 2022

Revised: 05 July 2022

Received: 23 February 2022

Published in TODAES Volume 28, Issue 2

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Cited By

Zhou HLi YXiong XZhou P(2024)A Transferable GNN-based Multi-Corner Performance Variability Modeling for Analog ICs2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473858(411-416)Online publication date: 22-Jan-2024
https://doi.org/10.1109/ASP-DAC58780.2024.10473858

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