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Chiplet Placement for 2.5D IC with Sequence Pair Based Tree and Thermal Consideration

Published: 31 January 2023 Publication History

Abstract

This work develops an efficient chiplet placer with thermal consideration for 2.5D ICs. Combining the sequence-pair based tree, branch-and-bound method, and advanced placement/pruning techniques, the developed placer can find the solution fast with the optimized total wirelength (TWL) on half-perimeter wirelength (HPWL). Additionally, with the post placement procedure, the placer reduces maximum temperatures with slight increase of wirelength. Experimental results show that the placer can not only find better optimized TWL (reducing 1.035% HPWL) but also speed up at most two orders of magnitude than the prior art. With thermal consideration, the placer can reduce the maximum temperature up to 8.214 °C with an average 5.376% increase of TWL.

References

[1]
M.-F. Chen, F.-C. Chen, W.-C. Chiou, and C. Doug, "System on integrated chips (SoIC) for 3D heterogeneous integration," in IEEE ECTC, 2019.
[2]
2D vs. 2.5D vs. 3D ICs, https://www.eetimes.com/2d-vs-2-5d-vs-3d-ics-101/.
[3]
S. Naffziger, K. Lepak, M. Paraschou, and M. Subramony, "2.2 AMD chiplet architecture for high-performance server and desktop products," in IEEE ISSCC, 2020.
[4]
M.-S. Lin, T.-C. Huang, C.-C. Tsai, K.-H. Tam, C.-H. Hsieh, T. Chen, W.-H. Huang, J. Hu, Y.-C. Chen, S. K. Goel, C.-M. Fu, S. Rusu, C.-C. Li, S.-Y. Yang, M. Wong, S.-C. Yang, and F. Lee, "A 7nm 4GHz Arm®-core-based CoWoS® chiplet design for high performance computing," in Symposium on VLSI Circuits, 2019.
[5]
R. Chaware, K. Nagarajan, and S. Ramalingam, "Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer," in IEEE ECTC, 2012.
[6]
Y.-K. Ho and Y. W. Chang, "Multiple chip planning for chip-interposer codesign," in Proc. DAC, 2013.
[7]
W. H. Liu, M. S. Chang, and T. C. Wang, "Floorplanning and signal assignment for silicon interposer-based 3D ICs," in Proc. DAC, 2014.
[8]
S. Osmolovskyi, J. Knechtel, I. L. Markov, and J. Lienig, "Optimal die placement for interposer-based 3D ICs," in Proc. ASP-DAC, 2018.
[9]
A. Coskun, F. Eris, A. Joshi, A. B. Kahng, Y. Ma, A. Narayan, and V. Srinivas, "Cross-layer co-optimization of network design and chiplet placement in 2.5-D systems," IEEE TCAD, vol. 39, no. 12, pp. 5183--5196, 2020.
[10]
Y. Ma, L. Delshadtehrani, C. Demirkiran, J. L. Abellan, and A. Joshi, "TAP-2.5D: A thermally-aware chiplet placement methodology for 2.5D systems," in Proc. DATE, 2021.
[11]
H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, "VLSI module placement based on rectangle-packing by the sequence-pair," IEEE TCAD, vol. 15, no. 12, pp. 1518--1524, 1996.
[12]
R. Chandra, L. Dagum, D. Kohr, R. Menon, D. Maydan, and J. McDonald, Parallel programming in OpenMP. Morgan kaufmann, 2001.
[13]
T. L. Bergman, T. L. Bergman, F. P. Incropera, D. P. Dewitt, and A. S. Lavine, Fundamentals of heat and mass transfer. John Wiley & Sons, 2011.
[14]
Y.-K. Cheng, C.-H. Tsai, C.-C. Teng, and S.-M. S. Kang, Electrothermal analysis of VLSI systems. Springer Science & Business Media, 2000.
[15]
S. S.-Y. Liu, R.-G. Luo, S. Aroonsantidecha, C.-Y. Chin, and H.-M. Chen, "Fast thermal aware placement with accurate thermal analysis based on green function," IEEE TVLSI, vol. 22, no. 6, pp. 1404--1415, 2013.
[16]
SuperLU 5.3.0, https://portal.nersc.gov/project/sparse/superlu/.
[17]
ANSYS Icepak, https://www.ansys.com/products/electronics/ansys-icepak.
[18]
S. Osmolovskyi and Jens Lienig, "Placement framework for interposer-based 3D ICs," 2017, https://www.ifte.de/english/research/interposer-design/index.html.
[19]
MCNC benchmark, https://s2.smu.edu/~manikas/Benchmarks/MCNC_Benchmark_Netlists.html.
[20]
J. Cong, J. Wei, and Y. Zhang, "A thermal-driven floorplanning algorithm for 3D ICs," in Proc. ICCAD, 2004.

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  • (undefined)Thermal-Aware Chiplet Placement for 2.5D ICs with Sequence Pair Based TreeACM Transactions on Design Automation of Electronic Systems10.1145/3716893

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          cover image ACM Conferences
          ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference
          January 2023
          807 pages
          ISBN:9781450397834
          DOI:10.1145/3566097
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          Published: 31 January 2023

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          Author Tags

          1. 2.5D IC
          2. chiplet placement
          3. sequence pair
          4. thermal

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