Jincong Lu
ABSTRACT
In this paper, we propose a novel approach for the real-time estimation of chip-level spatial power maps for commercial Google Coral M.2 TPU chips based on a machine-learning technique for the first time. The new method can enable the development of more robust runtime power and thermal control schemes to take advantage of spatial power information such as hot spots that are otherwise not available. Different from the existing commercial multi-core processors in which real-time performance-related utilization information is available, the TPU from Google does not have such information. To mitigate this problem, we propose to use features that are related to the workloads of running different deep neural networks (DNN) such as the hyperparameters of DNN and TPU resource information generated by the TPU compiler. The new approach involves the offline acquisition of accurate spatial and temporal temperature maps captured from an external infrared thermal imaging camera under nominal working conditions of a chip. To build the dynamic power density map model, we apply generative adversarial networks (GAN) based on the workload-related features. Our study shows that the estimated total powers match the manufacturer's total power measurements extremely well. Experimental results further show that the predictions of power maps are quite accurate, with the RMSE of only 4.98mW/mm2, or 2.6% of the full-scale error. The speed of deploying the proposed approach on an Intel Core i7-10710U is as fast as 6.9ms, which is suitable for real-time estimation.
- "Critical Reliability Challenges for The International Technology Roadmap for Semiconductors (ITRS)," 2003. In International Sematech Technology Transfer Document 03024377A-TR, 2003.Google Scholar
- H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, and D. Burger, "Dark silicon and the end of multicore scaling," Micro, IEEE, vol. 32, pp. 122--134, May 2012.Google ScholarDigital Library
- M. Taylor, "A landscape of the new dark silicon design regime," IEEE/ACM International Symposium on Microarchitecture, vol. 33, pp. 8--19, October 2013.Google Scholar
- K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, "Temperature-aware microarchitecture," in Proc. Intl. Symp. on Computer Architecture, 2006.Google Scholar
- J. Kong, S. W. Chung, and K. Skadron, "Recent thermal management techniques for microprocessors," ACM Comput. Surv., vol. 44, pp. 13:1--13:42, jun 2012.Google ScholarDigital Library
- S. Sadiqbatcha, J. Zhang, H. Zhao, H. Amrouch, J. Hankel, and S. X.-D. Tan, "Post-silicon heat-source identification and machine-learning-based thermal modeling using infrared thermal imaging," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2020.Google Scholar
- R. Joseph and M. Martonosi, "Run-time power estimation in high-performance microprocessors," in Proc. Int. Symp. on Low Power Electronics and Design (ISLPED), pp. 135--140, 2001.Google Scholar
- C. Isci and M. Martonosi, "Runtime power monitoring in high-end processors: Methodology and empirical data," in Proceedings of MICRO, 2003.Google Scholar
- W. Wu, L. Jin, J. Yang, P. Liu, and S. X.-D. Tan, "Efficient power modeling and software thermal sensing for runtime temperature monitoring," ACM Trans. on Design Automation of Electronics Systems, vol. 12, no. 3, pp. 1--29, 2007.Google ScholarDigital Library
- K. Dev, A. N. Nowroz, and S. Reda, "Power mapping and modeling of multi-core processors," in International Symposium on Low Power Electronics and Design (ISLPED), pp. 39--44, Sept 2013.Google Scholar
- X. Wang, S. Farsiu, P. Milanfar, and A. Shakouri, "Power trace: An efficient method for extracting the power dissipation profile in an ic chip from its temperature map," IEEE Transactions on Components and Packaging Technologies, vol. 32, no. 2, pp. 309--316, 2009.Google ScholarCross Ref
- R. Cochran, A. N. Nowroz, and S. Reda, "Post-silicon power characterization using thermal infrared emissions," in Proc. Int. Symp. on Low Power Electronics and Design (ISLPED), (New York, NY, USA), pp. 331--336, ACM, 2010.Google Scholar
- S. Paek, W. Shin, J. Sim, and L. Kim, "Powerfield: A probabilistic approach for temperature-to-power conversion based on markov random field theory," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 10, pp. 1509--1519, 2013.Google ScholarDigital Library
- A. Nowroz, G. Woods, and S. Reda, "Power mapping of integrated circuits using ac-based thermography," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, pp. 1398--1409, aug 2013.Google ScholarDigital Library
- F. Beneventi, A. Bartolini, P. Vivet, and L. Benini, "Thermal analysis and interpolation techniques for a logic+ wideio stacked dram test chip," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 4, pp. 623--636, 2016.Google ScholarDigital Library
- S. Reda, K. Dev, and A. Belouchrani, "Blind identification of thermal models and power sources from thermal measurements," IEEE Sensors Journal, vol. 18, pp. 680--691, Jan 2018.Google ScholarCross Ref
- J. Zhang, S. Sadiqbatcha, M. O'Dea, H. Amrouch, and S. X.-D. Tan, "Full-chip power density and thermal map characterization for commercial microprocessors under heat sink cooling," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1--1, 2021.Google Scholar
- S. Sadiqbatcha, J. Zhang, H. Amrouch, and S. X.-D. Tan, "Real-time full-chip thermal tracking: A post-silicon, machine learning perspective," IEEE Transactions on Computers, 2021.Google ScholarDigital Library
- Intel, "Intel Performance Counter Monitor (PCM)." https://software.intel.com/en-us/articles/intel-performance-counter-monitor.Google Scholar
- J. Zhang, S. Sadiqbatcha, W. Jin, and S. X. . Tan, "Accurate power density map estimation for commercial multi-core microprocessors," in 2020 Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 1085--1090, 2020.Google Scholar
- H. Amrouch and J. Henkel, "Lucid infrared thermography of thermally-constrained processors," in 2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 347--352, July 2015.Google Scholar
- S. Reda, K. Dev, and A. Belouchrani, "Blind identification of thermal models and power sources from thermal measurements," IEEE Sensors Journal, vol. 18, no. 2, pp. 680--691, 2018.Google ScholarCross Ref
- M. Abadi et al., "TensorFlow: Large-scale machine learning on heterogeneous systems," 2015. Software available from tensorflow.org.Google Scholar
- N. Ahmed, T. Natarajan, and K. R. Rao, "Discrete cosine transform," IEEE Transactions on Computers, vol. C-23, pp. 90--93, Jan 1974.Google Scholar
- "Edge TPU Compiler." Available from coral.ai/docs/edgetpu/compiler.Google Scholar
- I. Goodfellow, J. Pouget-Abadie, M. Mirza, B. Xu, D. Warde-Farley, S. Ozair, A. Courville, and Y. Bengio, "Generative adversarial nets," in Advances in Neural Information Processing Systems 27 (Z. Ghahramani, M. Welling, C. Cortes, N. D. Lawrence, and K. Q. Weinberger, eds.), pp. 2672--2680, Curran Associates, Inc., 2014.Google Scholar
- M. Mirza and S. Osindero, "Conditional Generative Adversarial Nets," arXiv e-prints, p. arXiv:1411.1784, Nov. 2014.Google Scholar
- M. Arjovsky, S. Chintala, and L. Bottou, "Wasserstein GAN," arXiv e-prints, p. arXiv:1701.07875, Dec. 2017.Google Scholar
Index Terms
- Learning Based Spatial Power Characterization and Full-Chip Power Estimation for Commercial TPUs
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