Polling-Based Memory Interface
Authors: 
Trung Le, Zhao Zhang, Zhichun ZhuAuthors Info & Claims
Trung Le, Zhao Zhang, Zhichun ZhuAuthors Info & ClaimsArticle No.: 47, Pages 1 - 23
Abstract
Non-volatile memory has been extensively researched as the alternative for a DRAM-based system; however, the traditional memory controller cannot efficiently track and schedule operations for all the memory devices in heterogeneous systems due to different timing requirements and complex architecture supports of various memory technologies. To address this issue, we propose a hybrid memory architecture framework called POMI (POlling-based Memory Interface). It uses a small buffer chip inserted on each DIMM (Dual In-line Memory Module) to decouple operation scheduling from the controller to enable the support for diverse memory technologies in the system. Unlike the conventional DRAM-based system, POMI uses a polling-based memory bus protocol for communication and to resolve any bus conflicts between memory modules. The buffer chip on each DIMM will provide feedback information to the main memory controller so that the polling overhead is trivial. We propose two unique designs. The first one adds additional bus lines for sending the feedback information, and the second one utilizes the Command/Address bus. The framework provides several benefits: a technology-independent memory system, higher parallelism, and better scalability. Our experimental results show that POMI can efficiently support both homogeneous and heterogeneous systems. Compared with the conventional DDR4-2400 implementation, our scheme improves the performance of memory-intensive workloads by 3.7% on average. Compared with an existing interface for hybrid memory systems, Twin-Load, it also improves performance by 22.0% on average for memory-intensive workloads.
References
[1]
N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, and S. K. Reinhardt. 2006. The M5 simulator: Modeling networked systems. IEEE Micro 26, 4 (July2006), 52–60.
[2]
K. Chandrasekar, B. Akesson, and K. Goossens. 2011. Improved power modeling of DDR SDRAMs. In Proceedings of the 2011 14th Euromicro Conference on Digital System Design. Architectures, Methods, and Tools. (DSD’11). 99–108.
[3]
Standard Performance Evaluation Corporation. 2019. SPEC CPU2006 and CPU2017. Available at http://www.spec.org.
[4]
Zehan Cui, Tianyue Lu, Sally A. McKee, Mingyu Chen, Haiyang Pan, and Yuan Ruan. 2016. Twin-Load: Bridging the gap between conventional direct-attached and buffer-on-board memory systems. In Proceedings of the 2nd International Symposium on Memory Systems. 164–176.
[5]
Rajagopalan Desikan, Charles R. Lefurgy, Stephen W. Keckler, and Doug Burger. 2002. On-Chip MRAM as a High-Bandwidth, Low-Latency Replacement for DRAM Physical Memories. Technical Report TR-02-47. University of Texas at Austin.
[6]
G. Dhiman, R. Ayoub, and T. Rosing. 2009. PDRAM: A hybrid PRAM and DRAM main memory system. In Proceedings of the 2009 46th ACM/IEEE Design Automation Conference. 664–669.
[7]
K. Fang, L. Chen, Z. Zhang, and Z. Zhu. 2011. Memory architecture for integrating emerging memory technologies. In Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques. 403–412.
[8]
Tae Jun Ham, Bharath K. Chelepalli, Neng Xue, and Benjamin C. Lee. 2013. Disintegrated control for energy-efficient and heterogeneous memory systems. In Proceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA’13). 424–435.
[9]
Andreas Hansson, Neha Agarwal, Aasheesh Kolli, Thomas Wenisch, and Aniruddha N. Udipi. 2014. Simulating DRAM controllers for future system architecture exploration. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS’14). 201–210.
[10]
Joseph Izraelevitz, Jian Yang, Lu Zhang, Juno Kim, Xiao Liu, Amirsaman Memaripour, Yun Joon Soh, et al. 2019. Basic performance measurements of the Intel Optane DC persistent memory module. arxiv:1903.05714 [cs.DC].
[11]
Joe Jeddeloh and Brent Keeth. 2012. Hybrid memory cube new DRAM architecture increases density and performance. In Proceedings of the 2012 Symposium on VLSI Technology (VLSIT’12). 87–88.
[12]
Trung Le, Zhao Zhang, and Zhichun Zhu. 2021. POMI: Polling-based memory interface for hybrid memory system. In Proceedings of the 2021 IEEE 39th International Conference on Computer Design (ICCD’21). 447–455. DOI:
[13]
Benjamin C. Lee, Engin Ipek, Onur Mutlu, and Doug Burger. 2009. Architecting phase change memory as a scalable DRAM alternative. In Proceedings of the 36th Annual International Symposium on Computer Architecture. 2–13.
[14]
Kevin Lim, Parthasarathy Ranganathan, Jichuan Chang, Chandrakant Patel, Trevor Mudge, and Steven Reinhardt. 2008. Understanding and designing new server architectures for emerging warehouse-computing environments. In Proceedings of the 35th Annual International Symposium on Computer Architecture. 315–326.
[15]
MetaRAM Inc.2015. MetaRAM Product Brief. Retrieved December 10, 2022 from http://www.metaram.com/pdf/briefs/MetaRAM_DDR3_PB.pdf.
[16]
Micron Technology Inc. 2015. CCMTD-1725822587-9875. Retrieved December 10, 2022 from https://www.micron.com/-/media/client/global/documents/products/data-sheet/dram/ddr4/8gb_ddr4_sdram.pdf.
[17]
M. Poremba and Y. Xie. 2012. NVMain: An architectural-level main memory simulator for emerging non-volatile memories. In Proceedings of the 2012 IEEE Computer Society Annual Symposium on VLSI. 392–397.
[18]
B. Pourshirazi, M. V. Beigi, Z. Zhu, and G. Memik. 2018. WALL: A writeback-aware LLC management for PCM-based main memory systems. In Proceedings of the 2018 Design, Automation, and Test in Europe Conference and Exhibition (DATE’18). 449–454.
[19]
Moinuddin K. Qureshi, John Karidis, Michele Franceschini, Vijayalakshmi Srinivasan, Luis Lastras, and Bulent Abali. 2009. Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture. 14–23.
[20]
Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, and Jude A. Rivers. 2009. Scalable high performance main memory system using phase-change memory technology. In Proceedings of the 36th Annual International Symposium on Computer Architecture. 24–33.
[21]
Muhammad M. Rafique and Zhichun Zhu. 2019. FAPS-3D: Feedback-directed adaptive page management scheme for 3D-stacked DRAM. In Proceedings of the International Symposium on Memory Systems. 373–382.
[22]
Scott Rixner, William J. Dally, Ujval J. Kapasi, Peter Mattson, and John D. Owens. 2000. Memory access scheduling. In Proceedings of the 27th Annual International Symposium on Computer Architecture. 128–138.
[23]
IEEE Computer Society. 2019. Intel Optane data center persistent memory. In Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS’19). IEEE, Los Alamitos, CA, i–xxv.
[24]
Shuang Song, Qinzhe Wu, Steven Flolid, Joseph Dean, Reena Panda, and Junyong Deng. 2018. Experiments with SPEC CPU 2017: Similarity, Balance, Phase Behavior and SimPoints. Technical Report TR-180515-01. University of Texas at Austin.
[25]
G. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen. 2009. A novel architecture of the 3D stacked MRAM L2 cache for CMPs. In Proceedings of the 2009 IEEE 15th International Symposium on High Performance Computer Architecture. 239–249.
[26]
Synopsys Corp.2022. Synopsys Design Compiler. Retrieved December 10, 2022 from https://www.synopsys.com/implementation-and-signoff/rtl-synthesis-test/dc-ultra.html.
[27]
The CXL Consortium.2021. CXL Specification. Retrieved December 10, 2022 from https://www.computeexpresslink.org/spec-landing.
[28]
UMC Library. 2022. UMC Free Standard Cell Library.Retrieved December 10, 2022 from https://www.faraday-tech.com/freelib/.
[29]
B. Ganesh, A. Jaleel, D. Wang and B. Jacob. 2007. Fully-Buffered DIMM memory architectures: Understanding mechanisms, overheads and scaling. IEEE 13th International Symposium on High Performance Computer Architecture, Scottsdale, AZ, 109–120. DOI:
[30]
Chengning Wang, Dan Feng, Wei Tong, Jingning Liu, Zheng Li, Jiayi Chang, Yang Zhang, et al. 2019. Cross-point resistive memory: Nonideal properties and solutions. ACM Trans. Des. Autom. Electron. Syst. 24, 4 (June2019), Article 46, 37 pages.
[31]
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ram Rajamony, and Yuan Xie. 2009. Hybrid cache architecture with disparate memory technologies. SIGARCH Comput. Archit. News (June2009), 34–45.
[32]
Hongzhong Zheng, Jiang Lin, Zhao Zhang, Eugene Gorbatov, Howard David, and Zhichun Zhu. 2008. Mini-Rank: Adaptive DRAM architecture for improving memory power efficiency. In Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture. 210–221.
[33]
Hongzhong Zheng, Jiang Lin, Zhao Zhang, and Zhichun Zhu. 2009. Decoupled DIMM: Building high-bandwidth memory system using low-speed DRAM devices. In Proceedings of the 36th Annual International Symposium on Computer Architecture. 255–266.
[34]
Ping Zhou, Bo Zhao, Jun Yang, and Youtao Zhang. 2009. A durable and energy efficient main memory using phase change memory technology. SIGARCH Comput. Archit. News 37, 3 (June2009), 14–23.
Index Terms
- Polling-Based Memory Interface
Recommendations
An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main Memory
A long battery life is a first-class design objective for mobile devices, and main memory accounts for a major portion of total energy consumption. Moreover, the energy consumption from memory is expected to increase further with ever-growing demands for ...
CAR: Securing PCM Main Memory System with Cache Address Remapping
ICPADS '12: Proceedings of the 2012 IEEE 18th International Conference on Parallel and Distributed SystemsPhase Change Memory (PCM) has emerged as a promising alternative of DRAM to provide energy-efficient and high-capacity memory for high performance servers. A new DRAM + PCM hybrid memory architecture has been proposed to leverage PCM's high density and ...
A hybrid memory architecture supporting fine-grained data migration
AbstractHybrid memory systems composed of dynamic random access memory (DRAM) and Non-volatile memory (NVM) often exploit page migration technologies to fully take the advantages of different memory media. Most previous proposals usually migrate data at a ...
Comments
Information & Contributors
Information
Published In
May 2023
456 pages
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].
Publisher
Association for Computing Machinery
New York, NY, United States
Journal Family
Publication History
Published: 10 May 2023
Online AM: 02 December 2022
Accepted: 07 November 2022
Revised: 29 September 2022
Received: 29 June 2022
Published in TODAES Volume 28, Issue 3
Check for updates
Author Tags
Qualifiers
- Research-article
Funding Sources
- National Science Foundation
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 173Total Downloads
- Downloads (Last 12 months)42
- Downloads (Last 6 weeks)2
Reflects downloads up to 01 Mar 2025
Other Metrics
Citations
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign inFull Access
View options
View or Download as a PDF file.
PDFeReader
View online with eReader.
eReaderFull Text
View this article in Full Text.
Full TextHTML Format
View this article in HTML Format.
HTML Format