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Design and Implementation of A Cache Adapted to the LoongArch Architecturert

Published: 15 March 2023 Publication History

Abstract

A cache adapted to the LoongArch architecture is designed and implemented using the FPAG platform. A simple and performance balanced Cache module is designed and implemented. The design of the read and write data paths of the Cache module is given, and a state machine is designed and implemented for the logical control of the Cache module. The interaction interface between the Cache and the CPU is designed. The CPU pipeline adaptation method for Cache in hit and unhit cases is given. The processing flow of UnCache access is given. Cache-related instructions in the LoongArch instruction set are implemented. The test results show that the scheme meets the design requirements. Cache is simple and effective, and is suitable as a case study for initial understanding of Cache functionality and structure.

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EITCE '22: Proceedings of the 2022 6th International Conference on Electronic Information Technology and Computer Engineering
October 2022
1999 pages
ISBN:9781450397148
DOI:10.1145/3573428
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 March 2023

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Author Tags

  1. CPU
  2. Cache
  3. FPGA
  4. LoongArch

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EITCE 2022

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Overall Acceptance Rate 508 of 972 submissions, 52%

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