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Two-stage Pipelined SRAM Design Based on 14nm FinFET Process

Published: 15 March 2023 Publication History

Abstract

In this paper, we propose a two-stage pipeline architecture for Static Random Memories (SRAM), which can reduce the decoder delay and thus effectively improve the memory operation speed. The proposed two-stage pipeline architecture divides the SRAM in the conventional architecture into two parts, the decoder and the read/write path, by a hierarchical approach and uses registers to connect these two parts. Simulation results using SMIC 14nm FinFET devices show that for a high-speed SRAM of 512words*16bits, the access speed of the array is improved by 21% compared to the SRAM under the conventional architecture. This design not only implements the read/write function of the two-stage pipelined SRAM, but also provides some optimization of its performance.

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EITCE '22: Proceedings of the 2022 6th International Conference on Electronic Information Technology and Computer Engineering
October 2022
1999 pages
ISBN:9781450397148
DOI:10.1145/3573428
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 March 2023

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Author Tags

  1. 14nm FinFET
  2. High Speed
  3. Pipeline
  4. SRAM

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EITCE 2022

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Overall Acceptance Rate 508 of 972 submissions, 52%

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