Yuan Lou
ABSTRACT
In this paper, we propose a two-stage pipeline architecture for Static Random Memories (SRAM), which can reduce the decoder delay and thus effectively improve the memory operation speed. The proposed two-stage pipeline architecture divides the SRAM in the conventional architecture into two parts, the decoder and the read/write path, by a hierarchical approach and uses registers to connect these two parts. Simulation results using SMIC 14nm FinFET devices show that for a high-speed SRAM of 512words*16bits, the access speed of the array is improved by 21% compared to the SRAM under the conventional architecture. This design not only implements the read/write function of the two-stage pipelined SRAM, but also provides some optimization of its performance.
- Joshi R V, Ziegler M M. Low Power Design From Moore to AI for nm Era: Invited Paper[C]// 2019 MIXDES - 26th International Conference "Mixed Design of Integrated Circuits and Systems". 2019. FNM Surname (2018).Google Scholar
- Quan B, Zhang T , Chen T , Prediction table based management policy for STT-RAM and SRAM hybrid cache[M]. 2012.Google Scholar
- Terzioglu E, Afghahi M C. Diffusion replica delay circuit method: US, US6809971 B2[P]. 2004.Google Scholar
- Nakamura, K, Kuhara. A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator [J]. Solid-State Circuits, IEEE Journal of, 1994. Conference Name: ACM Woodstock conferenceGoogle Scholar
- Dimarco D, Balmer M, Freeman C, A 200 MHz 256 kB second level cache with 1.6 GB/s data bandwidth[C]// 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC. IEEE, 2002.Google Scholar
- Pilo H, Lamphier S, Towler F, A 300 MHz, 3.3 V 1 Mb SRAM fabricated in a 0.5 /spl mu/m CMOS process[C]// 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC. IEEE, 1996.Google Scholar
- Lopacinski L, Hasani A, Panic G, Ultra high speed 802.11n LDPC decoder with seven-stage pipeline in 28 nm CMOS[C]// 2022 IEEE 95th Vehicular Technology Conference: (VTC2022-Spring). 2022.Google Scholar
- Stimming B, Konstantinos A. Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders. 2016.Google Scholar
- Patel P K, Malik M, Gupta T K. Design of an ultralow power CNTFET based 9T SRAM with shared BL and half select free techniques[J]. International Journal of Numerical Modelling, 2019, 32(2): e2511.1-e2511.9.Google ScholarCross Ref
- Chatziantoniou P, Tsigkanos A, Theodoropoulos D, An Efficient Architecture and High-Throughput Implementation of CCSDS-123.0-B-2 Hybrid Entropy Coder Targeting Space-Grade SRAM FPGA Technology[J]. 2022.Google Scholar
Index Terms
- Two-stage Pipelined SRAM Design Based on 14nm FinFET Process
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