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PASoC: A Predictable Accelerator-rich SoC

Published: 09 May 2023 Publication History

Abstract

We present a model of a predictable accelerator-rich system-on-chip (PASoC) for safety-critical systems. The PASoC allows the integration of multiple coherent agents to interact with each other over a shared memory bus. These agents can be a cluster of cache-coherent homogeneous cores, and fully or one-way coherent hardware accelerators. PASoC supports predictable cache coherence within the cluster of cores, and across agents. The former uses linear cache coherence, and the latter uses a modified version of predictable MSI. We analyze the per-request worst-case latency, a memory request from any of the agents can experience in the PASoC. Finally, we present some observations based on our analysis that can help in future designs of PASoCs.

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cover image ACM Conferences
CPS-IoT Week '23: Proceedings of Cyber-Physical Systems and Internet of Things Week 2023
May 2023
419 pages
ISBN:9798400700491
DOI:10.1145/3576914
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Published: 09 May 2023

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Author Tags

  1. Hardware accelerators
  2. Predictability
  3. Safety-critical systems
  4. SoCs

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