Shubam Gupta
ABSTRACT
Assertion Based Verification is a design methodology that integrates Formal Methods as part of the design process. As each module is designed, the designer expresses the functional, structural and interface requirements of the module as logical formulas called assertions. These assertions are then verified using simulation and/or formal verification. This paper aims at studying the effectiveness of applying formal verification during Assertion Based Verification in the development of VHDL design for a VME-bus for safety applications in nuclear reactors. Assertions for the VHDL modules developed were expressed in PSL, and were proved using three industrially successful and popular formal verification algorithms – Bounded Model Checking, K-Induction, and Property Driven Reachability, implemented in an open-source verification tool, Yosys. Our experiments revealed that Property Driven Reachability completely outperforms K-Induction in all the cases. Bounded Model Checking for a few hundred clock cycles helped us in finding a number of important, but subtle bugs, which were missed by traditional simulation, at the cost of a justifiable increase in design effort towards writing assertions.
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Index Terms
- Assertion Based Verification using Yosys: A Case Study from Nuclear Domain
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