Abstract
With the rapidly growing demand for system-level integration, package substrates have become one of the most important carriers in semiconductor industry. Fine pitch ball grid array (FBGA) packaging is a widely used technology thanks to its relative cost-effectiveness compared to other advanced packaging technologies. In addition, it is also widely used in space-constrained applications, such as mobile and handheld devices. These packaging substrate interconnections are usually customized by layout engineers taking many complex and stringent design rules into consideration. However, fully net-by-net manual design for FBGA is time-consuming and error-prone. In this article, we propose an integer linear programming (ILP)-based router for wire-bonding FBGA packaging design. Our ILP formulation not only can handle design-dependent constraints but also take the problem of mismatched via dimension into account, which is caused by the mechanical processes and greatly increases design complexity. In addition to the ILP formulation for substrate routing, three optimization stages and several ILP constraint reduction techniques are also developed to boost the run time of ILP solver. Experimental results indicate that the proposed framework can achieve high routing completion rates, which could effectively reduce the cycle time of substrate layout design. In addition, in combination with the proposed optimization strategies, 278× speedup can be achieved compared to the ILP constraint optimized router.
- [1] William Greig. 2007. Integrated Circuit Packaging, Assembly, and Interconnections. Springer.Google Scholar
- [2] Internal discussion with Win Wen, Sam Hsu, Meilin Hsieh, and Vincent Hsu, Package Design Engineering, ASE Group ChungLi, 2018–2021.Google Scholar
- [3] C. C. Tsai, C. M. Wang, and S. J. Chen. 1998. NEWS: A net-even-wiring system for the routing on a multilayer PGA package. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17, 2 (1998), 182–189.Google Scholar
- [4] S. S. Chen, J. J. Chen, T. Y. Lee, C. C. Tsai, and S. J. Chen. 1999. A new approach to the ball grid array package routing. IEICE Transactions on Fundamentals E82-A, 11 (1999), 2599–2608.Google Scholar
- [5] Y. Kubo and A. Takahashi. 2006. Global routing by iterative improvements for two-layer ball grid array packages. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, 4 (2006), 725–733.Google ScholarDigital Library
- [6] Y. Tomioka and A. Takahashi. 2009. Routability driven via assignment method for 2-layer ball grid array packages. IEICE Transactions on Fundamentals E92-A, 6 (2009), 1433–1441.Google Scholar
- [7] J. T. Yan. 2011. IO connection assignment and RDL routing for flip-chip designs. ACM Transactions on Design Automation of Electronic Systems 16, 4 (2011), 1–20.Google Scholar
- [8] R. J. Lee and H. M. Chen. 2013. A study of row-based area-array I/O design planning in concurrent chip-package design flow. ACM Transactions on Design Automation of Electronic Systems 18, 2 (2013), 1–19.Google ScholarDigital Library
- [9] J. W. Fang, C. H. Hsu, and Y. W. Chang. 2009. An integer linear programming based routing algorithm for flip-chip design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28, 1 (2009), 98–110.Google ScholarDigital Library
- [10] C. W. Lin, P. W. Lee, Y. W. Chang, C. F. Shen, and W. C. Tseng. 2012. An efficient pre-assignment routing algorithm for flip-chip designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, 6 (2012), 878–889.Google Scholar
- [11] Gurobi Optimizer 8.1. Retrieved August 20, 2020 from http://www.gurobi.com/.Google Scholar
- [12] Cadence Allegro Package Designer 16.6. Retrieved August 20, 2020 from https://www.cadence.com/.Google Scholar
- [13] X. Jia, Y. Cai, Q. Zhou, and B. Yu. A multicommodity flow-based detailed router with efficient acceleration techniques. IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems 37, 1 (2018), 217–230.Google ScholarCross Ref
Index Terms
- ILP-based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package Design
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