ABSTRACT
Design Rule Checking (DRC) is one of the most important metrices in physical design procedure to evaluate quality of a detail route. The prediction of DRC violation (DRV) in the early stage can reduce the iterations of design procedure and improve the efficiency of the physical design closure. Several researchers have applied machine-learning techniques to predict the DRVs of a detail route at different design stages with various input features. In this paper, we proposed a machine learning model to predict DRVs with the information obtained after placement stage. Specifically, we build a ResNet-like CNN model to predict whether a DRV may occur in a targeted grid after detail route. Our features consist of not only quantified placement information but also layout-image features to take pin accessibility into account for better prediction result. Moreover, we apply an under-sampling technique to select critical training samples to improve the training efficiency. A series of experiments have been conducted and the results show that compared with previous works, our prediction result can outperform Fully Convolutional Network (FCN) based approaches.
- Cadence, Inc. Innovus Implementation System. https://www.cadence.com/en_US/home/tools/digital-design-and-signoff/soc-implementation-and-floorplanning/innovus-implementation-system.htmlGoogle Scholar
- Wen-Hao Liu, Cheng-Kok Koh, and Yih-Lang Li. 2013. Case study for placement solutions in ispd11 and dac12 routability-driven placement contests. In Proceedings of the 2013 ACM International symposium on Physical Design (ISPD '13). 114--119.Google ScholarDigital Library
- Vladimir Yutsis, Ismail S. Bustany, David Chinnery, Joseph R. Shinnerl, and Wen-Hao Liu. 2014. ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement. In Proceedings of the 2014 on International symposium on physical design (ISPD '14). 161--168.Google Scholar
- Wei-Ting J Chan, Yang Du, Andrew B Kahng, Siddhartha Nath, and Kambiz Samadi. 2016. BEOL stack-aware routability prediction from placement using data mining techniques. In 2016 IEEE 34th International Conference on Computer Design (ICCD). 41--48.Google ScholarCross Ref
- Wei-Tse Hung, Jun-Yang Huang, Yih-Chih Chou, Cheng-Hong Tsai, and Mango Chao. 2020. Transforming Global Routing Report into DRC Violation Map with Convolutional Neural Network. In Proceedings of the 2020 International Symposium on Physical Design (ISPD '20). 57--64.Google ScholarDigital Library
- Aysa Fakheri Tabrizi, Nima Karimpour Darav, Logan Rakai, Andrew Kennings and Laleh Behjat. 2017. Detailed routing violation prediction during placement using machine learning. In 2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). 1--4.Google ScholarCross Ref
- Aysa Fakheri Tabrizi, Nima Karimpour Darav, Shuchang Xu, Logan Rakai, Ismail Bustany, Andrew Kennings, and Laleh Behjat. 2018. A machine learning framework to identify detailed routing short violations from a placed netlist. In Proceedings of the 55th Annual Design Automation Conference (DAC '18). 1--6.Google ScholarDigital Library
- Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, and Henry Sheng. 2019. Pin Accessibility Prediction and Optimization with Deep Learning-based Pin Pattern Recognition. In Proceedings of the 56th Annual Design Automation Conference 2019 (DAC '19). 1--6.Google ScholarDigital Library
- Riadul Islam, Md. Asif Shahjalal. 2019. Soft voting-based ensemble approach to predict early stage DRC violations. In IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS). 1081--1084Google ScholarCross Ref
- Tao-Chun Yu, Shao-Yun Fang, Hsien-Shih Chiu, Kai-Shun Hu, Philip Hui-Yuh Tai, Cindy Chin-Fang Shen, and Henry Sheng. 2020. Lookahead Placement Optimization with Cell Library-based Pin Accessibility Prediction via Active Learning. In Proceedings of the 2020 International Symposium on Physical Design (ISPD '20). 65--72.Google ScholarDigital Library
- Rongjian Liang, Hua Xiang, Diwesh Pandey, Lakshmi Reddy, Shyam Ramji, Gi-Joon Nam, and Jiang Hu. 2020. DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network. In Proceedings of the 2020 International Symposium on Physical Design (ISPD '20). 135--142.Google ScholarDigital Library
- Chen-Chia Chang, Jingyu Pan, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chun-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, and Yiran Chen. 2021. Automatic Routability Predictor Development Using Neural Architecture Search. In 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD). 1--9.Google Scholar
- Wei-Ting J. Chan, Pei-Hsin Ho, Andrew B. Kahng, and Prashant Saxena. 2017. Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning. In Proceedings of the 2017 ACM on International Symposium on Physical Design (ISPD '17). 15--21.Google ScholarDigital Library
- Li-Chin Chen, Chien-Chia Huang, Yao-Lin Chang and Hung-Ming Chen. 2018. A learning-based methodology for routability prediction in placement. In 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). 1--4.Google ScholarCross Ref
- Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing Ren, Shao-Yun Fang, Yiran Chen, and Jiang Hu. 2018. RouteNet: Routability prediction for Mixed-Size Designs Using Convolutional Neural Network. In 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). 1--8.Google ScholarDigital Library
- Wei Zeng, Azadeh Davoodi, and Rasit Onur Topaloglu. 2020. Explainable DRC hotspot prediction with random forest and SHAP tree explainer. In Proceedings of the 23rd Conference on Design, Automation and Test in Europe (DATE '20). EDA Consortium, San Jose, CA, USA, 1151--1156.Google ScholarDigital Library
- Lin Li, Yici Cai, Qiang Zhou. 2021. An Efficient Approach for DRC Hotspot Prediction with Convolutional Neural Network. In 2021 IEEE International Symposium on Circuits and Systems (ISCAS). 1--5.Google Scholar
- Quan Zhou, Xueyan Wang, Zhongdong Qi, Zhuwei Chen, Qiang Zhou and Yici Cai. 2015. An accurate detailed routing routability prediction model in placement. In 2015 6th Asia Symposium on Quality Electronic Design (ASQED). 119--122.Google ScholarCross Ref
- Jingsong Chen, Jian Kuang, Guowei Zhao, Dennis J.-H. Huang, and Evangeline F. Y. Young. 2023. PROS 2.0: A plug-in for routability optimization and routed wirelength estimation using deep learning. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 164--177.Google Scholar
- Miaodi Su, Hongzhi Ding, Shaohong Weng, Changzhong Zou, Zhonghua Zhou, Yilu Chen, Jianli Chen, and Yao-Wen Chang. 2022. High-Correlation 3D Routability Estimation for Congestion-guided Global Routing. In 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC). 580--585.Google ScholarDigital Library
- Jonathan Long, Evan Shelhamer, and Trevor Darrell. 2015. Fully convolutional networks for semantic segmentation. In Proceedings of IEEE Conference on Computer Vision and Pattern Recognition (CVPR). 3431--3440Google ScholarCross Ref
Index Terms
- DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network
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