Aditya Anirudh Jonnalagadda
ABSTRACT
Posit number system is an emerging number system which aims to be a competitor to the existing IEEE floating-point number system. The posit number system aims to overcome certain inherent flaws associated with the floating-point system and improve the performance of VLSI arithmetic circuits. Recent studies indicate that posit number system has the potential to vastly improve the performance of deep neural network hardware. As a result, posit arithmetic has become an important area of research. Among all the arithmetic operations in computer arithmetic, the most frequently used is multiplication. Multiplication is ubiquitously used in applications varying from image processing, signal processing to neural networks and machine learning. Multiplication also has an extremely high cost in terms of power, area and delay and thus extensive research work goes into optimization of the above parameters. In this brief, two new multiplier designs based on the Modified Booth algorithm have been proposed- P1 and P2 with novel control logic circuits to reduce dynamic power dissipation. The proposed work also involves the design of a novel sign extension with lower gate count for the Modified Booth Algorithm. Results have indicated that the proposed designs P1 and P2 achieve an improvement of 24% and 22% respectively in the PDP over the existing designs.
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Index Terms
- Design of Energy Efficient Posit Multiplier
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