Yan Pi
ABSTRACT
With the successful application of hardware agile design methodology, it has become a big challenge to optimize the design in novelly defined intermediate representations (IR), such as FIRRTL. However, there is little work focusing on this challenge, or the optimization tasks are left to logic synthesizers by translating IRs into designs in hardware description languages (HDL).
In this paper, we propose a novel method based on equality saturation to optimize design in IR forms. For the given optimization goal, the proposed method is able to optimize a circuit in IR form with mixed word- and bit-level components. The promising experimental results show that the proposed method can really optimize a design in IR form. Furthermore, when taking the number of cells as the optimization goal, the proposed method could achieve up to 28.62% reduction when compared with FIRRTL native optimization techniques.
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Index Terms
- ESFO: Equality Saturation for FIRRTL Optimization
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