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TPNoC: An Efficient Topology Reconfigurable NoC Generator

Published: 05 June 2023 Publication History

Abstract

With the core count increasing in Chip to support various data-intensive workloads, Network-on-chip (NoC) has become the better solution for addressing on-chip interconnection. Various data-intensive workloads have different traffic patterns that require NoC with different topologies and microarchitectures. On the one hand, topology type selection has a great influence on the final performance, area, and energy. However, it is difficult to change the topology type in the traditional NoC RTL design process once it is determined. On the other hand, NoC platforms have many tunable micro-architecture design parameters, which require careful design space exploration to trade off performance advantages and overhead. Designing and validating each microarchitecture of NoCs to account for various trade-offs will greatly exacerbate the design cost issue.
We propose TPNoC, a topology reconfigurable NoC generator framework. The TPNoC framework is divided into parameterization, verification evaluation, and RTL generation stages, which can be reconfigured into plug-and-play NoC platforms with different topologies and microarchitectures according to the architect's configuration. Architects can efficiently use TPNoC to explore the best NoC for specific workloads. Through verification and evaluation experiments, we demonstrate that TPNoC can be efficiently reconfigured into different NoCs while maintaining high performance.

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  1. TPNoC: An Efficient Topology Reconfigurable NoC Generator

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      cover image ACM Conferences
      GLSVLSI '23: Proceedings of the Great Lakes Symposium on VLSI 2023
      June 2023
      731 pages
      ISBN:9798400701252
      DOI:10.1145/3583781
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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      Published: 05 June 2023

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      Author Tags

      1. modeling
      2. network-on-chip generator
      3. simulation

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      • Research-article

      Funding Sources

      • Science and Technology Commission of Shanghai Municipality Project
      • 62090025
      • 61929102
      • 62141407
      • 61974032

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      GLSVLSI '23
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      GLSVLSI '23: Great Lakes Symposium on VLSI 2023
      June 5 - 7, 2023
      TN, Knoxville, USA

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      Overall Acceptance Rate 312 of 1,156 submissions, 27%

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