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Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics

Published: 18 April 2023 Publication History

Abstract

3D flash memories have been widely developed to further increase the storage capacity of SSDs by vertically stacking multiple layers. However, this special physical structure brings new error characteristics. Existing studies have discovered that there exist significant Raw Bit Error Rate (RBER) variations among different layers and RBER similarity inside the same layer due to the manufacturing process. These error characteristics would introduce a new data reliability issue. Currently, Low-Density Parity-Check (LDPC) code has been widely used to ensure the data reliability of flash memories. It can provide stronger error correction capability for high RBERs by trading with longer read latency. Traditional LDPC codes designed for planar flash memories do not consider the layer RBER characteristics of 3D flash memories, which may induce sub-optimal read performance.
This article first investigates the effect of RBER characteristics of 3D flash memories on read performance and then obtains two observations. On one hand, we observe that LDPC read latencies are largely diverse in different flash layers and increase in diverse speeds along with data retention. This phenomenon is caused by the inter-layer RBER variation. On the other hand, we also compare RBERs between different pages of the same flash layer and observe that read latencies with LDPC codes are quite similar, which is caused by the intra-layer RBER similarity. Then, by exploiting these two observation results, this article proposes a Multi-Granularity LDPC (MG-LDPC) read method to adapt read latency increase characteristics across 3D flash layers. In detail, we design five LDPC decoding engines with varied read level increase granularity (higher level induces higher latency) and assign these engines to each layer dynamically according to prior information, or in a fixed way. A series of experimental results demonstrate that the fixed and dynamic MG-LDPC methods can reduce SSD read response time by 21% and 51% on average, respectively.

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  1. Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics

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    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 28, Issue 3
    May 2023
    456 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/3587887
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    Association for Computing Machinery

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    Publication History

    Published: 18 April 2023
    Online AM: 27 February 2023
    Accepted: 01 February 2023
    Revised: 04 January 2023
    Received: 04 September 2022
    Published in TODAES Volume 28, Issue 3

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    Author Tags

    1. 3D flash memories
    2. read performance
    3. Low-Density Parity-Check codes
    4. layer RBERs variation

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    • Shenzhen Fundamental Research Program
    • National Natural Science Foundation of China

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    • (2024)Modeling Retention Errors of 3D NAND Flash for Optimizing Data PlacementACM Transactions on Design Automation of Electronic Systems10.1145/365910129:4(1-24)Online publication date: 21-Jun-2024
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    • (2024)Adaptive Granularity Progressive LDPC Decoding for NAND Flash MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.333282943:4(1312-1316)Online publication date: 1-Apr-2024

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