Global Interconnect Optimization
Article No.: 72, Pages 1 - 24
Abstract
We propose a new comprehensive solution to global interconnect optimization. Traditional buffering algorithms mostly insert repeaters on a net-by-net basis based on slacks and possibly guided by global wires.
We show how to integrate routing congestion, placement congestion, global timing constraints, power consumption, and additional constraints into a single resource sharing formulation. The core of our algorithm is a new buffered routing subroutine. Given a net and Lagrangean resource prices for routing, timing, placement, and power, it computes a buffered Steiner tree. The resource sharing framework provides a special multiplicative price update for fast convergence.
Our algorithm is fast enough for practical instances. We demonstrate experimentally on 7nm microprocessor units that it significantly improves timing while reducing netlength and power consumption in an industrial design flow. Our implementation scales well under parallelization with up to 128 threads.
References
[1]
C. Albrecht, A. B. Khang, I. Mandoiu, and A. Zelikovsky. 2002. Floorplan evaluation with timing-driven global wireplanning, pin assignment and buffer/wire sizing. ASP-DAC ’02, (2002) 580–588.
[2]
C. J. Alpert, W.-K. Chow, K. Han, A. B. Kahng, Z. Li, D. Liu, and S. Venkatesh. 2018. Prim-Dijkstra revisited: Achieving superior timing-driven routing trees. ISPD’18, (2018) 10–17.
[3]
C. J. Alpert, J. H. Huangm, A. B. Kahng, and D. Karger. 1995. Prim-Dijkstra tradeoffs for improved performance-driven routing tree design. TCAD 14, 7 (1995) 890–896.
[4]
C. Bartoschek, S. Held, D. Rautenbach, and J. Vygen. 2009. Fast buffering for optimizing worst slack and resource consumption in repeater trees. ISPD ’09, (2009) 43–50.
[5]
D. Blankenburg. 2022. Resource sharing revisited: Local weak duality and optimal convergence. (ESA 2022, to appear), preprint: arXiv:2111.06820, (2022).
[6]
R. C. Carden and C.-K. Cheng. 1991. A global router using an efficient approximate multicommodity multiterminal flow algorithm. DAC ’91, (1991) 316–321.
[7]
G. Chen and E. F. Y. Young. 2019. SALT: Provably good routing topology by a novel Steiner shallow-light tree algorithm. IEEE TCAD 39, 6 (2019), 1217–1230.
[8]
J. Chuzhoy, A. Gupta, J. Naor, and A. Sinha. 2008. On the approximability of network design problems. ACM TALG 4, 2 (2008), 1–17.
[9]
S. Daboul, N. Hähnle, S. Held, and U. Schorr. 2018. Provably fast and near-optimum gate sizing. TCAD 37(12) (2018), 3163–3176.
[10]
S. Daboul, S. Held, B. Natura, and D. Rotter. 2019. Global interconnect optimization. ICCAD ’19 (2019), Article 1C.3.
[11]
W. Elmore. 1948. The transient response of damped linear networks with particular regard to wideband amplifiers. Journal of Applied Physics 19 (1948), 55–63.
[12]
S. Held, S. Müller, D. Rotter, R. Scheifele, V. Traub, and J. Vygen. 2017. Global routing with timing constraints. TCAD 37, 2 (2017), 406–419.
[13]
S. Held and B. Rockel. 2018. Exact algorithms for delay-bounded Steiner arborescences. DAC ’18, (2018) Article 44.
[14]
S. Held and D. Rotter. 2013. Shallow light Steiner arborescences with vertex delays. IPCO ’13 (2013), 996–1025.
[15]
M. Hrkić and J. Lillis. 2003. Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages. IEEE TCAD 22, 4 (2003), 481–491.
[16]
J. Hu, Y. Zhou, Y. Wei, S. Quay, L. Reddy, G. Tellez, and G.-J. Nam. 2018. Interconnect optimization considering multiple critical paths. ISPD’18 (2018), 132–138.
[17]
A. K. Kiefner. 2016. Minimizing path lengths in rectilinear Steiner minimum trees with fixed topology. Operations Research Letters 44, 6 (2016), 835–838.
[18]
Z. Li, C. J. Alpert, G.-J. Nam, C. Sze, N. Viswanathan, and N. Y. Zhou. 2012. Guiding a physical design closure system to produce easier-to-route designs with more predictable timing. DAC’ 12, (2012) 465–470.
[19]
Z. Li, C. J. Alpert, S. Hu, T. Muhmud, S. T. Quay, and P. G. Villarrubia. 2008. Fast interconnect synthesis with layer assignment. ISPD ’08, (2008) 71–77.
[20]
Z. Li, Y. Zhou, and W. Shi. 2012. \(O (mn)\) time algorithm for optimal buffer insertion of nets with m sinks. IEEE TCAD 31, 3 (2012), 437–441.
[21]
D. Liu, B. Yu, S. Chowdhury, and D. Z. Pan. 2018. TILA-S: Timing-driven incremental layer assignment avoiding slew violations. IEEE TCAD 37, 1 (2018), 231–244.
[22]
J. Lillis, C. K. Cheng, and T. T. Y. Lin. 1996. Optimal wire sizing and buffer insertion for low power and a generalized delay model. J. of Solid-State Circuits 31, 3 (1996), 436–447.
[23]
D. Müller, K. Radke, and J. Vygen. 2011. Faster min-max resource sharing in theory and practice. Math. Progr. Computation 3, 1 (2011), 1–35.
[24]
C. L. Ratzlaff and L. T. Pillage. 1994. RICE: Rapid interconnect circuit evaluation using AWE. TCAD 13 (1994), 763–776.
[25]
E. Shragowitz and S. Keel. 1987. A global router based on a multicommodity flow model. Integr. VLSI J. 5 (1987), 3–16.
[26]
T. Terlaky, A. Vannelli, and H. Zhang. 2008. On routing in VLSI design and communication networks. Discrete Applied Mathematics 156, 11 (2008), 2178–2194.
[27]
L. P. P. P. Van Ginneken. 1990. Buffer placement in distributed RC-tree networks for minimal Elmore delay. ISCAS (1990), 865–868.
[28]
Y. Wei, Z. Li, C. C. N. Sze, S. Hu, C. J. Alpert, S. S. Sapatnekar. 2013. CATALYST: Planning layer directives for effective design closure. DATE ’13 (2013), 1873–1878.
[29]
Y. Wei, C. Sze, N. Viswanathan, Z. Li, C. J. Alpert, L. Reddy, A. D. Huber, G. E. Téllez, D. Keller, and S. S. Sapatnekar. 2014. Techniques for scalable and effective routability evaluation. ACM Trans. Design Autom. Electr. Syst 19, 2 (2014), 17:1-17:37.
Index Terms
- Global Interconnect Optimization
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September 2023
475 pages
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Publication History
Published: 09 September 2023
Online AM: 09 March 2023
Accepted: 23 February 2023
Revised: 17 February 2023
Received: 18 August 2022
Published in TODAES Volume 28, Issue 5
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