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Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems

Published: 18 July 2023 Publication History

Abstract

This paper presents estimation and analysis of the higher order harmonics, power features, and real performance of flip-flop and master-slave latch topologies. This research article outlines the impact of transistor model quality and input signal selection on the estimate of higher order harmonic contents of switching waveform emitted by the digital integrated circuits. Highly integrated systems require accurate estimation of higher order harmonics to control noise. This work presents simulations of 12 kinds of flip-flop and latch topologies on different process technologies i.e., 28 nm, 45 nm, 65 nm, and 130 nm. It is implied that the steeper the spectrum roll-off, the fewer the contents of higher order harmonics. Results of 28 nm process design kit are improved compared to 45 nm, 65 nm, and 130 nm process design kits. Furthermore, the results of the comparison of representative flip-flop and latch topologies illustrate the advantage of the approach and the suitability for high performance and low power consumption.

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  • (2023)Exploring the impact of initial design techniques on area, timing, and power in technology mapped designs: A case study on 32-bit arithmetic logic unitInternational Journal of ADVANCED AND APPLIED SCIENCES10.21833/ijaas.2023.09.00810:9(68-74)Online publication date: Sep-2023

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  1. Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems

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        Published In

        cover image ACM Transactions on Design Automation of Electronic Systems
        ACM Transactions on Design Automation of Electronic Systems  Volume 28, Issue 4
        July 2023
        432 pages
        ISSN:1084-4309
        EISSN:1557-7309
        DOI:10.1145/3597460
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        Association for Computing Machinery

        New York, NY, United States

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        Publication History

        Published: 18 July 2023
        Accepted: 23 March 2023
        Revised: 21 February 2023
        Received: 25 November 2022
        Published in TODAES Volume 28, Issue 4

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        Author Tags

        1. Integrated circuits
        2. flip-flops
        3. latches
        4. high performance systems
        5. switching harmonics
        6. digital noise

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        • (2024)Modeling & Analysis of Quantum Confinement and Ballistic Transport Phenomena in 3D FinFET2024 21st International Conference on Mechatronics - Mechatronika (ME)10.1109/ME61309.2024.10789755(1-4)Online publication date: 4-Dec-2024
        • (2023)Exploring the impact of initial design techniques on area, timing, and power in technology mapped designs: A case study on 32-bit arithmetic logic unitInternational Journal of ADVANCED AND APPLIED SCIENCES10.21833/ijaas.2023.09.00810:9(68-74)Online publication date: Sep-2023

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