Physical design is the epicenter where the complexity of circuit system design at the billion-transistor scale meets the complexity of silicon fabrication at the nanometer scale. Such ever-increasing complexity makes physical design the most critical and challenging stage in the entire VLSI design flow. Despite a long time of active research and development, traditional algorithmic approaches such as nonlinear optimization have gradually lost steam under the heavy weight of physical design complexity, and are looking desperately for help from all possible directions.

Empowered by fast-growing cloud-scale computing power and Internet-scale data, machine learning technologies have made remarkable progress in innovation and broad adoptions across a wide range of application domains. Several seminal works have demonstrated encouraging results targeting various aspects of IC design stages. In particular, researchers have been actively pursuing machine learning methods to tackle key physical design problems covering both digital and analog circuits, such as floorplanning, placement, routing, parasitic extraction and modeling, gate sizing/buffering, post-silicon simulation, and design for manufacturing.

This special issue presents a collection of recent advances in machine learning technologies for VLSI physical design, covering key physical design issues including routing and placement, power delivery, gate sizing, interconnect analysis, reliability, manufacturability, and physical security, which are summarized as follows.

Placement and Routing. In “IMPRoVED: Integrated Method to Predict Post-Routing Setup Violations in Early Design Stages,” Krishna et al. focus on timing analysis, a critical yet time-consuming problem. They propose a random forest based method equipped with a set of new features, such as post-route buffer-bloat and cell sizing prediction, for fast timing delay and violation estimation. In “Routability Optimization of Extreme Aspect Ratio Design Through Non-Uniform Placement Utilization and Selective Flip-Flop Stacking,” Hyun et al. focus on the routability optimization problem for designs with extreme aspect ratios and high area utilization. They propose a set of techniques, including a CNN-based model to generate a non-uniform placement distribution for routability optimization, a flip-flop selection and stacking method for clock routing resource minimization, and A U-Net model with GAT for congestion estimation. In “Multi-Terminal Pathfinding in Practical VLSI Systems with Deep Neural Networks,” Utyamishev et al. tackle the multiterminal obstacle-avoiding pathfinding problem. They map the problem to an image manipulation task and solve the problem using a conditional generative adversarial network based approach.

Gate Sizing. In “DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI Graphs,” Cheng et al. tackle the discrete gate sizing problem using a directed graph convolutional network. The proposed method leverages the topological ordering of the timing graph and uses a node ordering aware recurrent message-passing scheme for embedding generation, which is then used for sequentially ordered delta-delay prediction using a teacher sampling-based mechanism.

Power Delivery. In “Routability-Driven Power/Ground Network Optimization Based on Machine Learning,” Huang et al. address the dynamic IR drop problem of the power/ground network. They propose a multi-task learning based method for worst dynamic IR drop prediction and neighboring routing congestion estimation. The authors demonstrate that the proposed method enables an optimized tradeoff between dynamic IR drop and routing resource utilization. In “Worst-Case Power Integrity Prediction Using a Convolutional Neural Network,” Dong et al. propose to use a neural network for worst-case power integrity prediction for a power delivery network. The authors propose to use current feature compression with careful feature engineering to optimize the scalability and efficiency of power integrity prediction. The authors demonstrate the efficacy of the proposed method for dynamic noise prediction and bump current prediction. In “ECO-GNN: Signoff Power Prediction Using Graph Neural Networks with Subgraph Approximation,” Lu et al. propose a graph neural network based Vth assignment method for fast and accurate signoff power optimization. The proposed method consists of a classification-based method for Vth assignment and a subgraph approximation method for power saving prediction.

Interconnect Analysis. In “CNN-Cap: Effective Convolutional Neural Network Based Capacitance Models for Interconnect Capacitance Extraction,” Yang et al. propose to use a convolutional neural network to deliver fast and accurate parasitic capacitance estimation. The proposed method uses grid-based data representation to support both 2D pattern structure and 3D window structure modeling, and decouple the estimation of total capacitance and coupling capacitance as two separate and less-challenging subproblems. The authors demonstrate good model accuracy with orders of magnitude prediction speedup using GPU acceleration.

Reliability. In “A Deep Learning Framework for Solving Stress-Based Partial Differential Equations in Electromigration Analysis,” Hou et al. propose a physics-informed neural network method to tackle the electromigration-induced reliability analysis problem. The proposed method, as a mesh-free approach, uses a deep neural network equipped with physical constraints of EM kinetics. The authors use the proposed method to analyze the stress migration of multi-segment interconnect trees and demonstrate satisfactory accuracy and computational savings.

Manufacturability. In “CmpCNN: CMP Modeling with Transfer Learning CNN Architecture,” Zhang et al. propose to use a deep neural network to tackle the chemical mechanical polishing modeling (CMP) problem. The proposed deep model takes the binary image of chip layout and its density information as input and predicts the CMP topography height. The authors also propose to use transfer learning to support different CMP process variants and circuit categories.

Physical Security. In “A Problem-Tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions,” Aseeri et al. propose to attack feed-forward PUF (FF PUF) by introducing a custom-tailored neural network based adversarial model trained using in-silicon implementation. The ability to attack FF PUF can help the PUF and IoT designers improve the existing designs to resist possible risks.

Finally, we would like to thank all the reviewers who contributed their expertise and time to review manuscripts submitted to the special issue. In addition, for comments and questions regarding this article, please contact the guest editor team.