skip to main content
10.1145/3599691.3603414acmconferencesArticle/Chapter ViewAbstractPublication PageshotstorageConference Proceedingsconference-collections
research-article

A Study of Invalid Programming in 3D QLC NAND Flash Memories

Published: 10 July 2023 Publication History

Abstract

3D QLC NAND flash memories are now widely applied in storage systems due to their high density. They adopt the two-step programming strategy to avoid severe program interference. This strategy results in a non-trivial time period between the two programming steps, during which the data could be invalidated from update operations. The second programming step might be performed on invalid data, which is defined as invalid programming in this work. We investigate the severity of the invalid programming issue by presenting the elapsed time between the two steps and the ratio of pages that suffer from invalid programming. By varying several parameters of the evaluated storage system, we present that the issue is common in 3D QLC-based storage systems. Finally, we introduce two pilot solutions to deal with the issue in our future work.

References

[1]
Wanik Cho, Jongseok Jung, Jongwoo Kim, Junghoon Ham, Sangkyu Lee, Yujong Noh, Dauni Kim, Wanseob Lee, Kayoung Cho, Kwanho Kim, et al. 2022. A 1-Tb, 4b/Cell, 176-Stacked-WL 3D-NAND Flash Memory with Improved Read Latency and a 14.8 Gb/mm2 Density. In 2022 IEEE International Solid-State Circuits Conference (ISSCC), Vol. 65. IEEE, 134--135.
[2]
Guiqiang Dong, Ningde Xie, and Tong Zhang. 2010. On the use of soft-decision error-correction codes in NAND flash memory. IEEE Transactions on Circuits and Systems I: Regular Papers 58, 2 (2010), 429--439.
[3]
Akira Goda. 2021. Recent progress on 3D NAND flash technologies. Electronics 10, 24 (2021), 3156.
[4]
Duwon Hong, Myungsuk Kim, Geonhee Cho, Dusol Lee, and Jihong Kim. 2022. GuardedErase: Extending SSD Lifetimes by Protecting Weak Wordlines. In 20th USENIX Conference on File and Storage Technologies (FAST 22). 133--146.
[5]
Hwang Huh, Wanik Cho, Jinhaeng Lee, Yujong Noh, Yongsoon Park, Sunghwa Ok, Jongwoo Kim, Kayoung Cho, Hyunchul Lee, Geonu Kim, et al. 2020. 13.2 a 1TB 4b/cell 96-stacked-wl 3d NAND flash memory with 30mb/s program throughput using peripheral circuit under memory cell array technique. In 2020 IEEE International Solid-State Circuits Conference-(ISSCC). IEEE, 220--221.
[6]
Shehbaz Jaffer, Kaveh Mahdaviani, and Bianca Schroeder. 2022. Improving the Reliability of Next Generation SSDs using WOM-v Codes. In 20th USENIX Conference on File and Storage Technologies (FAST 22). 117--132.
[7]
Myoungsoo Jung, Jie Zhang, Ahmed Abulila, Miryeong Kwon, Narges Shahidi, John Shalf, Nam Sung Kim, and Mahmut Kandemir. 2017. SimpleSSD: Modeling solid state drives for holistic system simulation. IEEE Computer Architecture Letters 17, 1 (2017), 37--41.
[8]
Ali Khakifirooz, Eduardo Anaya, Sriram Balasubrahrmanyam, Geoff Bennett, Daniel Castro, John Egler, Kuangchan Fan, Rifat Ferdous, Kartik Ganapathi, Omar Guzman, et al. 2023. A 1.67 Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-NAND Technology and Featuring a 23.3 Gb/mm2 Bit Density. In 2023 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 27--29.
[9]
Ali Khakifirooz, Sriram Balasubrahmanyam, Richard Fastow, Kristopher H Gaewsky, Chang Wan Ha, Rezaul Haque, Owen W Jungroth, Steven Law, Aliasgar S Madraswala, Binh Ngo, et al. 2021. 30.2 a 1TB 4b/cell 144-tier floating-gate 3d-NAND flash memory with 40mb/s program throughput and 13.8 GB/mm 2 bit density. In 2021 IEEE International Solid-State Circuits Conference (ISSCC), Vol. 64. IEEE, 424--426.
[10]
Junkyum Kim, Myeonggu Kang, Yunki Han, Yang-Gon Kim, and Lee-Sup Kim. 2023. OptimStore: In-Storage Optimization of Large Scale DNNs with On-Die Processing. In 2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE, 611--623.
[11]
Seungjae Lee, Chulbum Kim, Minsu Kim, Sung-min Joe, Joonsuc Jang, Seungbum Kim, Kangbin Lee, Jisu Kim, Jiyoon Park, Han-Jun Lee, et al. 2018. A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput. In 2018 IEEE International Solid-State Circuits Conference-(ISSCC). IEEE, 340--342.
[12]
Qiao Li, Liang Shi, Yufei Cui, and Chun Jason Xue. 2019. Exploiting asymmetric errors for LDPC decoding optimization on 3D NAND flash memory. IEEE Trans. Comput. 69, 4 (2019), 475--488.
[13]
Shicheng Li, Longfei Luo, Yina Lv, and Liang Shi. 2022. Latency Aware Page Migration for Read Performance Optimization on Hybrid SSDs. In 2022 IEEE 11th Non-Volatile Memory Systems and Applications Symposium (NVMSA). IEEE, 33--38.
[14]
Caiyin Liu, Min Lv, Yubiao Pan, Hao Chen, Yongkun Li, Cheng Li, and Yinlong Xu. 2018. LCR: Load-aware cache replacement algorithm for flash-based SSDs. In 2018 IEEE International Conference on Networking, Architecture and Storage (NAS). IEEE, 1--10.
[15]
Weihua Liu, Fei Wu, Xiang Chen, Meng Zhang, Yu Wang, Xiangfeng Lu, and Changsheng Xie. 2022. Characterization Summary of Performance, Reliability, and Threshold Voltage Distribution of 3D Charge-Trap NAND Flash Memory. ACM Transactions on Storage (TOS) 18, 2 (2022), 1--25.
[16]
Weihua Liu, Fei Wu, Meng Zhang, Yifei Wang, Zhonghai Lu, Xiangfeng Lu, and Changsheng Xie. 2019. Characterizing the reliability and threshold voltage shifting of 3D charge trap NAND flash. In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 312--315.
[17]
Chihiro Matsui, Chao Sun, and Ken Takeuchi. 2017. Design of hybrid SSDs with storage class memory and NAND flash memory. Proc. IEEE 105, 9 (2017), 1812--1821.
[18]
Junoh Moon, Mincheol Kang, Wonyoung Lee, and Soontae Kim. 2022. Salvaging runtime bad blocks by skipping bad pages for improving SSD performance. In 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 576--579.
[19]
Dushyanth Narayanan, Austin Donnelly, and Antony Rowstron. 2008. Write off-loading: Practical power management for enterprise storage. ACM Transactions on Storage (TOS) 4, 3 (2008), 1--23.
[20]
Ki-Tae Park, Myounggon Kang, Doogon Kim, Soon-Wook Hwang, Byung Yong Choi, Yeong-Taek Lee, Changhyun Kim, and Kinam Kim. 2008. A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories. IEEE Journal of Solid-State Circuits 43, 4 (2008), 919--928.
[21]
Seon-yeong Park, Dawoon Jung, Jeong-uk Kang, Jin-soo Kim, and Joonwon Lee. 2006. CFLRU: a replacement algorithm for flash memory. In Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems. 234--241.
[22]
Ted Pekny, Luyen Vu, Jeff Tsai, Dheeraj Srinivasan, Erwin Yu, Jonathan Pabustan, Joe Xu, Srinivas Deshmukh, Kim-Fung Chan, Michael Piccardi, et al. 2022. A 1-Tb density 4b/cell 3D-NAND flash on 176-tier technology with 4-independent planes for read using CMOS-under-the-array. In 2022 IEEE International Solid-State Circuits Conference (ISSCC), Vol. 65. IEEE, 1--3.
[23]
Borja Peleato, Rajiv Agarwal, John M Cioffi, Minghai Qin, and Paul H Siegel. 2015. Adaptive read thresholds for NAND flash. IEEE Transactions on Communications 63, 9 (2015), 3069--3081.
[24]
Noboru Shibata, Kazushige Kanda, Takahiro Shimizu, Jun Nakai, Osamu Nagao, Naoki Kobayashi, Makoto Miakashi, Yasushi Nagadomi, Tomoaki Nakano, Takahisa Kawabe, et al. 2019. A 1.33-Tb 4-bit/cell 3-D flash memory on a 96-word-line-layer technology. IEEE Journal of Solid-State Circuits 55, 1 (2019), 178--188.
[25]
Noboru Shibata, Hiroshi Maejima, Katsuaki Isobe, Kiyoaki Iwasa, Michio Nakagawa, Masaki Fujiu, Takahiro Shimizu, Mitsuaki Honma, Satoru Hoshi, Toshimasa Kawaai, et al. 2008. A 70 nm 16 Gb 16-level-cell NAND flash memory. IEEE Journal of Solid-State Circuits 43, 4 (2008), 929--937.
[26]
Youngseop Shim, Myungsuk Kim, Myoungjun Chun, Jisung Park, Yoona Kim, and Jihong Kim. 2019. Exploiting process similarity of 3D flash memory for high performance SSDs. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture. 211--223.
[27]
Jiguang Wan, Wei Wu, Ling Zhan, Qing Yang, Xiaoyang Qu, and Changsheng Xie. 2017. DEFT-Cache: A cost-effective and highly reliable SSD cache for RAID storage. In 2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 102--111.
[28]
Gala Yadgar, MOSHE Gabel, Shehbaz Jaffer, and Bianca Schroeder. 2021. SSD-based workload characteristics and their performance implications. ACM Transactions on Storage (TOS) 17, 1 (2021), 1--26.
[29]
Sangjin Yoo and Dongkun Shin. 2020. Reinforcement Learning-Based SLC Cache Technique for Enhancing SSD Write Performance. In Hot-Storage.
[30]
Jie Zhang and Myoungsoo Jung. 2020. Zng: Architecting gpu multiprocessors with new flash for scalable data analysis. In 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA). IEEE, 1064--1075.

Cited By

View all
  • (2024)Reliability Impacts Among Neighboring Wordlines on 3D QLC NAND Flash2024 13th Non-Volatile Memory Systems and Applications Symposium (NVMSA)10.1109/NVMSA63038.2024.10693657(1-6)Online publication date: 21-Aug-2024
  • (2024)Midas Touch: Invalid-Data Assisted Reliability and Performance Boost for 3d High-Density Flash2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00057(657-670)Online publication date: 2-Mar-2024

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
HotStorage '23: Proceedings of the 15th ACM Workshop on Hot Topics in Storage and File Systems
July 2023
131 pages
ISBN:9798400702242
DOI:10.1145/3599691
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the owner/author(s).

Sponsors

In-Cooperation

  • USENIX

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 10 July 2023

Check for updates

Qualifiers

  • Research-article

Funding Sources

  • the National Natural Science Foundation of China
  • the Natural Science Foundation of Xiamen

Conference

HotStorage '23
Sponsor:

Acceptance Rates

Overall Acceptance Rate 34 of 87 submissions, 39%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)167
  • Downloads (Last 6 weeks)11
Reflects downloads up to 16 Feb 2025

Other Metrics

Citations

Cited By

View all
  • (2024)Reliability Impacts Among Neighboring Wordlines on 3D QLC NAND Flash2024 13th Non-Volatile Memory Systems and Applications Symposium (NVMSA)10.1109/NVMSA63038.2024.10693657(1-6)Online publication date: 21-Aug-2024
  • (2024)Midas Touch: Invalid-Data Assisted Reliability and Performance Boost for 3d High-Density Flash2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA57654.2024.00057(657-670)Online publication date: 2-Mar-2024

View Options

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Figures

Tables

Media

Share

Share

Share this Publication link

Share on social media