Guy Lemieux
ABSTRACT
In FPGAs, the internal connections in a cluster of lookup tables (LUTs) are often fully-connected like a full crossbar. Such a high degree of connectivity makes routing easier, but has significant area overhead. This paper explores the use of sparse crossbars as a switch matrix inside the clusters between the cluster inputs and the LUT inputs. We have reduced the switch densities inside these matrices by 50% or more and saved from 10 to 18% in area with no degradation to critical-path delay. To compensate for the loss of routability, increased compute time and spare cluster inputs are required. Further investigation may yield modest area and delay reductions.
- 1.E. Ahmed. The effect of logic block granularity on deepsubmicron FPGA performance and density. Master's thesis, Department of Electrical and Computer Engineering, University of Toronto, 2001.Google Scholar
- 2.E. Ahmed and J. Rose. The effect of LUT and cluster size on deep-submicron FPGA performance and density. In ACM/SIGDA Int'l. Symp. on FPGAs, pages 3-12, 2000. Google ScholarDigital Library
- 3.V. Betz and J. Rose. VPR: A new packing, placement and routing tool for FPGA research. In Field-Programmable Logic, pages 213-222, 1997. Google ScholarDigital Library
- 4.V. Betz, J. Rose, and A. Marquardt. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, Boston, 1999. Google ScholarDigital Library
- 5.J. Cong and Y. Ding. FlowMap: An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. IEEE Transactions on Computer-Aided Design, pages 1-12, January 1994.Google Scholar
- 6.W. Elmore. The transient response of damped linear networks with particular regard to wideband amplifiers. Journal of Applied Physics, pages 55-63, January 1948.Google ScholarCross Ref
- 7.C. B. Laboratory. LGSynth93 suite. http://www.cbl.ncsu.edu/www/.Google Scholar
- 8.G. Lemieux, P. Leventis, and D. Lewis. Generating highly-routable sparse crossbars for PLDs. In ACM/SIGDA Int'l. Symp. on FPGAs, pages 155-164, Monterey, CA, February 2000. Google ScholarDigital Library
- 9.A. Marquardt, V. Betz, and J. Rose. Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density. In ACM/SIGDA Int'l. Symp. on FPGAs, pages 37-46, 1999. Google ScholarDigital Library
- 10.A. Marquardt, V. Betz, and J. Rose. Timing-driven placement for FPGAs. In ACM/SIGDA Int'l. Symp. on FPGAs, pages 203-213, 2000. Google ScholarDigital Library
- 11.M. I. Masud. FPGA routing structures: A novel switch block and depopulated interconnect matrix architectures. Master's thesis, Department of Electrical and Computer Engineering, University of British Columbia, December 1999.Google Scholar
- 12.J. Rose and S. Brown. Flexibility of interconnection structures in field-programmable gate arrays. IEEE Journal of Solid State Circuits, 26(3):277-282, March 1991.Google ScholarCross Ref
- 13.E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli. SIS: A system for sequential circuit analysis. Technical Report UCB/ERL M92/41, University of California, Berkeley, May 1992.Google Scholar
- 14.M. Sheng and J. Rose. Mixing buffers and pass transistors in FPGA routingarchitectures. In ACM/SIGDA Int'l. Symp. on FPGAs, 2001. Google ScholarDigital Library
Index Terms
- Using sparse crossbars within LUT
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