ABSTRACT
RISC-V is an open source modular and scalable emerging instruction set. As the RISC-V architecture gradually matures in the field of contemporary chips, the RISC-V software ecosystem is also gradually prospering. Some mainstream tool chains and operating systems have supported RISC-V architecture since the beginning, and now gradually support multiple RISC-V expansion directive. Although there are many works dedicated to advancing RISC-V instruction extensions to adapt to various scenarios under different computing power requirements, and exploring the RISC-V software ecosystem, there is no work on existing tool chains and operating systems to extend RISC-V Conduct systematic research and conclusions on the support of the instructions. The purpose of this paper is to systematically and comprehensively investigate and summarize the adaptation of tool chain and operating system to RISC-V extended instructions, including some extensions defined in the RISC-V instruction set specification and some customized Define extensions. In this article, we mainly elaborate on our research from four aspects: operating system, compiler, simulator, and verification tools.
- [n. d.]. AndeSight IDE. http://www.andestech.com/en/products-solutions/andesight-ide/Google Scholar
- [n. d.]. Debian – The Universal Operating System. https://www.debian.org/Google Scholar
- [n. d.]. FreeRTOS - Market leading RTOS. https://www.freertos.org/Google Scholar
- [ [n. d.]. IAR Embedded Workbench for RISC-V. https://www.iar.com/products/architectures/risc-v/iar-embedded-workbench-for-risc-v/Google Scholar
- [n. d.]. Play with OpenEuler on VisionFive. https://gitee.com/samuel_yuan/riscv-openeuler-visionfiveGoogle Scholar
- [n. d.]. RIOT - The friendly Operating System for the Internet of Things. https://www.riot-os.org/Google Scholar
- rt-thread [n. d.]. RT-Thread | An Open Source Embedded Real-time Operating System. https://www.rt-thread.io/Google Scholar
- safertos [n. d.]. SAFERTOS, the safety certified RTOS. https://www.highintegritysystems.com/safertos/Google Scholar
- zephyr [n. d.]. Zephyr Project. https://www.zephyrproject.org/Google Scholar
- Abdelrahman Adel, Dina Saad, Mahmoud Abd El Mawgoed, Mohamed Sharshar, Zyad Ahmed, Hala Ibrahim, and Hassan Mostafa. 2021. Implementation and Functional Verification of RISC-V Core for Secure IoT Applications. In 2021 International Conference on Microelectronics (ICM). 254–257. https://doi.org/10.1109/ICM52667.2021.9664926Google ScholarCross Ref
- Özlem Altinay and Berna Örs. 2021. Instruction Extension of RV32I and GCC Back End for Ascon Lightweight Cryptography Algorithm. In 2021 IEEE International Conference on Omni-Layer Intelligent Systems (COINS). 1–6. https://doi.org/10.1109/COINS51742.2021.9524190Google ScholarCross Ref
- Imad Al Assir, Mohamad El Iskandarani, Hadi Rayan Al Sandid, and Mazen A. R. Saghir. 2021. Arrow: A RISC-V Vector Accelerator for Machine Learning Inference. CoRR abs/2107.07169 (2021). arXiv:2107.07169Google Scholar
- Yi-Ru Chen, Hui-Hsin Liao, Chia-Hsuan Chang, Che-Chia Lin, Chao-Lin Lee, Yuan-Ming Chang, Chun-Chieh Yang, and Jenq-Kuen Lee. 2020. Experiments and optimizations for TVM on RISC-V Architectures with P Extension. In 2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 1–4.Google ScholarCross Ref
- Joao Mario Domingos, Nuno Neves, Nuno Roma, and Pedro Tomás. 2021. Unlimited vector extension with data streaming support. In 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). IEEE, 209–222.Google ScholarDigital Library
- Peter Yuen Ho Hin, Xiongfei Liao, Jin Cui, Andrea Mondelli, Thannirmalai Muthukaruppan Somu, and Naxin Zhang. 2021. Supporting RISC-V Full System Simulation in gem5. (2021).Google Scholar
- Heng Lin, Piyo Chen, Yuan-Shin Hwang, and Jenq-Kuen Lee. 2019. Devise rust compiler optimizations on RISC-V architectures with SIMD instructions. In Proceedings of the 48th International Conference on Parallel Processing: Workshops. 1–7.Google ScholarDigital Library
- B Madhavan, A Kamerish, and R Manimegalai. 2020. ATGP_RISC-V: Automation of Test Generator using Pluggy for RISC-V Architecture. In 2020 Third International Conference on Smart Systems and Inventive Technology (ICSSIT). IEEE, 484–491.Google ScholarCross Ref
- David Mallasén, Raul Murillo, Alberto A Del Barrio, Guillermo Botella, Luis Piñuel, and Manuel Prieto-Matias. 2022. PERCIVAL: Open-source posit RISC-V core with quire capability. IEEE Transactions on Emerging Topics in Computing 10, 3 (2022), 1241–1252.Google ScholarCross Ref
- Nuno Neves, Joao Mario Domingos, Nuno Roma, Pedro Tomas, and Gabriel Falcao. 2022. Compiling for Vector Extensions with Stream-based Specialization. IEEE Micro (2022).Google Scholar
- Boria Perez, Alexander Fell, and John D. Davis. 2021. Coyote: An Open Source Simulation Tool to Enable RISC- V in HPC. In 2021 Design, Automation and Test in Europe Conference and Exhibition (DATE). 130–135. https://doi.org/10.23919/DATE51398.2021.9474080Google ScholarCross Ref
- Mehrdad Poorhosseini, Wolfgang Nebel, and Kim Grüttner. 2020. A Compiler Comparison in the RISC-V Ecosystem. In 2020 International Conference on Omni-layer Intelligent Systems (COINS). 1–6. https://doi.org/10.1109/COINS49042.2020.9191411Google ScholarCross Ref
- Fabien Portas and Frédéric Pétrot. 2022. Fast simulation of future 128-bit architectures. In 2022 Design, Automation and Test in Europe Conference and Exhibition (DATE). 1131–1134. https://doi.org/10.23919/DATE54114.2022.9774706Google ScholarCross Ref
- Cristóbal Ramírez, César Alejandro Hernández, Oscar Palomar, Osman Unsal, Marco Antonio Ramírez, and Adrián Cristal. 2020. A risc-v simulator and benchmark suite for designing and evaluating vector architectures. ACM Transactions on Architecture and Code Optimization (TACO) 17, 4 (2020), 1–30.Google ScholarDigital Library
- Miguel Silva, Tiago Gomes, and Sandro Pinto. 2021. Leveraging RISC-V to build an open-source (hardware) OS framework for reconfigurable IoT devices. CARRV2021 6 (2021).Google Scholar
- Giuseppe Tagliavini, Stefan Mach, Davide Rossi, Andrea Marongiu, and Luca Benini. 2019. Design and Evaluation of SmallFloat SIMD extensions to the RISC-V ISA. In 2019 Design, Automation and Test in Europe Conference and Exhibition (DATE). 654–657. https://doi.org/10.23919/DATE.2019.8714897Google ScholarCross Ref
- Jiayi Wang, Nianxiong Tan, Yangfan Zhou, Ting Li, and Junhu Xia. 2020. A UVM Verification Platform for RISC-V SoC from Module to System Level. In 2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM). 242–246. https://doi.org/10.1109/ICICM50929.2020.9292250Google ScholarCross Ref
- Xi Wang, John D. Leidel, Brody Williams, Alan Ehret, Miguel Mark, Michel A. Kinsy, and Yong Chen. 2021. xBGAS: A Global Address Space Extension on RISC-V for High Performance Computing. 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS) (2021), 454–463.Google ScholarCross Ref
- Yinan Xu, Zihao Yu, Dan Tang, Guokai Chen, Lu Chen, Lingrui Gou, Yue Jin, Qianruo Li, Xin Li, Zuojun Li, Jiawei Lin, Tong Liu, Zhigang Liu, Jiazhan Tan, Huaqiang Wang, Huizhe Wang, Kaifan Wang, Chuanqi Zhang, Fawang Zhang, Linjuan Zhang, Zifei Zhang, Yangyang Zhao, Yaoyang Zhou, Yike Zhou, Jiangrui Zou, Ye Cai, Dandan Huan, Zusong Li, Jiye Zhao, Zihao Chen, Wei He, Qiyuan Quan, Xingwu Liu, Sa Wang, Kan Shi, Ninghui Sun, and Yungang Bao. 2022. Towards Developing High Performance RISC-V Processors Using Agile Methodology. In 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO). 1178–1199. https://doi.org/10.1109/MICRO56248.2022.00080Google ScholarDigital Library
- Chun-Chieh Yang, Yi-Ru Chen, Hui-Hsin Liao, Yuan-Ming Chang, and Jenq-Kuen Lee. 2022. Auto-Tuning Fixed-Point Precision with TVM on RISC-V Packed SIMD Extension. ACM Transactions on Design Automation of Electronic Systems (2022).Google Scholar
Index Terms
- RISC-V ISA Extension Toolchain Supports: A Survey
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