Physical design automation has been a key enabling technology for high-quality and cost-effective integrated circuit design. Recent advances in integrated circuit manufacturing processes and applications have brought lots of new challenges to physical design. Moore's Law continues to push the limits of process lithography into the deep nanometer regime for better performance, power efficiency, transistor density, and cost. Additionally, More-than-Moore technologies add diverse devices and adopt heterogeneous integration to achieve better system-level power-performance cost tradeoffs and higher design functionality. Thus, tools need to handle complex design constraints and objectives of emerging process technologies like advanced lithography, 2.5D/3D heterogeneous integration, FinFET/multi-gate devices, and photonic devices. Physical design is also a critical design stage to satisfy the increasingly stringent requirements in power, timing, and reliability. Given the ever-increasing design scale and complexity, it is important for physical design tools to take advantage of computing platforms employing multi-core, GPU, FPGA, and AI hardware acceleration. These new challenges necessitate the research and development of new physical design techniques and methodology.
In this special issue, we have 10 articles covering state-of-the-art efforts to conquer these challenges. We hope you will enjoy them and find them as interesting and useful as we did. The special section opens with three articles on different tasks at placement. The first article, “
A Generalized Methodology for Well Island Generation and Well-Tap Insertion in Analog/Mixed-Signal Layouts,” by Gopalakrishnan et al., addresses well-island and well-tap insertion that is required for analog layout. The authors propose a solution where these steps are done during placement, allowing the placer to incorporate these alterations in its optimization metrics. “
Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5 D Heterogeneous FPGAs,” by Wei et al., provides the first analytical placement algorithm for 2.5D heterogeneous FPGAs to simultaneously minimize the number of inter-die sidelobe level signals and intra-die clocking resources, based on 3D Poisson's equation and proximal group
alternating direction method of multipliers (
ADMM). A fast computation of 3D Poisson's equation and a parameter updating scheme are presented to accelerate the convergence of the optimization problem. “
A Fast Optimal Double Row Legalization Algorithm,” by Hougardy et al., improves the legalization step in standard-cell placement by minimizing cell displacement for both single-row and double-row height cells, assuming a fixed left-to-right ordering within each row. In doing so, the authors do not artificially bound the maximum cell movement and can guarantee to find an optimal solution with minimum cell displacement.
The next two articles discuss global buffer insertion and congestion estimation for the routing stage. The article “
Global Interconnect Optimization,” by Daboul et al., shows a new approach to solve the global buffer insertion problem, by balancing a multitude of different objectives via a resource sharing framework. The authors tested this new technique on 7 nm microprocessor units in an industrial design flow, showing timing improvement while reducing both net length and power consumption. “
MEDUSA: A Multi-resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing” presents a congestion estimation framework that consists of a feature extraction and an image encoding algorithm, which produces “hyper-images” from ASIC netlists, and solves the information interfering issue. The MEDUSA framework also presents a machine learning network that directly uses the encoded “hyper-images” as input, to perform global routing congestion estimation. Two versions of MEDUSA were developed and integrated with two routers (CU-GR-M and UBC-Route): MEDUSA-3D works on 3D routing and the latest ICCAD2018/2019 benchmarks; and MEDUSA-2D applies 2D routing on legacy ISPD2008 benchmarks. The authors show that MEDUSA has better congestion estimation accuracy compared with previous works.
We would like to thank all the authors and reviewers for their tremendous contributions. This special issue would not be possible without their outstanding and timely work. Special thanks go to the TODAES editor-in-chief Professor X. Sharon Hu, and senior associate editor Professor Joerg Henkel, for their support of this special section, and Megan Shuler for her editorial efforts. We hope that the selected articles in this special issue will be valuable to the community.
Iris Hui-Ru Jiang
National Taiwan University
David Chinnery
Siemens Digital Industries Software
Gracieli Posser
Cadence Design Systems
Jens Lienig
Dresden University of Technology
Guest Editors