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Introduction to the Special Section on Advances in Physical Design Automation

Published: 09 September 2023 Publication History
Physical design automation has been a key enabling technology for high-quality and cost-effective integrated circuit design. Recent advances in integrated circuit manufacturing processes and applications have brought lots of new challenges to physical design. Moore's Law continues to push the limits of process lithography into the deep nanometer regime for better performance, power efficiency, transistor density, and cost. Additionally, More-than-Moore technologies add diverse devices and adopt heterogeneous integration to achieve better system-level power-performance cost tradeoffs and higher design functionality. Thus, tools need to handle complex design constraints and objectives of emerging process technologies like advanced lithography, 2.5D/3D heterogeneous integration, FinFET/multi-gate devices, and photonic devices. Physical design is also a critical design stage to satisfy the increasingly stringent requirements in power, timing, and reliability. Given the ever-increasing design scale and complexity, it is important for physical design tools to take advantage of computing platforms employing multi-core, GPU, FPGA, and AI hardware acceleration. These new challenges necessitate the research and development of new physical design techniques and methodology.
In this special issue, we have 10 articles covering state-of-the-art efforts to conquer these challenges. We hope you will enjoy them and find them as interesting and useful as we did. The special section opens with three articles on different tasks at placement. The first article, “A Generalized Methodology for Well Island Generation and Well-Tap Insertion in Analog/Mixed-Signal Layouts,” by Gopalakrishnan et al., addresses well-island and well-tap insertion that is required for analog layout. The authors propose a solution where these steps are done during placement, allowing the placer to incorporate these alterations in its optimization metrics. “Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5 D Heterogeneous FPGAs,” by Wei et al., provides the first analytical placement algorithm for 2.5D heterogeneous FPGAs to simultaneously minimize the number of inter-die sidelobe level signals and intra-die clocking resources, based on 3D Poisson's equation and proximal group alternating direction method of multipliers (ADMM). A fast computation of 3D Poisson's equation and a parameter updating scheme are presented to accelerate the convergence of the optimization problem. “A Fast Optimal Double Row Legalization Algorithm,” by Hougardy et al., improves the legalization step in standard-cell placement by minimizing cell displacement for both single-row and double-row height cells, assuming a fixed left-to-right ordering within each row. In doing so, the authors do not artificially bound the maximum cell movement and can guarantee to find an optimal solution with minimum cell displacement.
The next two articles discuss global buffer insertion and congestion estimation for the routing stage. The article “Global Interconnect Optimization,” by Daboul et al., shows a new approach to solve the global buffer insertion problem, by balancing a multitude of different objectives via a resource sharing framework. The authors tested this new technique on 7 nm microprocessor units in an industrial design flow, showing timing improvement while reducing both net length and power consumption. “MEDUSA: A Multi-resolution Machine Learning Congestion Estimation Method for 2D and 3D Global Routing” presents a congestion estimation framework that consists of a feature extraction and an image encoding algorithm, which produces “hyper-images” from ASIC netlists, and solves the information interfering issue. The MEDUSA framework also presents a machine learning network that directly uses the encoded “hyper-images” as input, to perform global routing congestion estimation. Two versions of MEDUSA were developed and integrated with two routers (CU-GR-M and UBC-Route): MEDUSA-3D works on 3D routing and the latest ICCAD2018/2019 benchmarks; and MEDUSA-2D applies 2D routing on legacy ISPD2008 benchmarks. The authors show that MEDUSA has better congestion estimation accuracy compared with previous works.
Two articles seek novel parameter tuning techniques to enhance VLSI and 3D IC design flows. “Boosting VLSI Design Flow Parameter Tuning with R and om Embedding and Multi-objective Trust-Region Bayesian Optimization,” by Zheng et al., examines parameter tuning for VLSI design flows. The authors reduce the number of variables for the optimization algorithm via random embedding and explore Pareto-optimal tool parameter configurations in parallel by multi-objective trust-region Bayesian optimization. “A PPA Study of Reinforced Placement Parameter Autotuning: Pseudo-3 Dvs. True-3D Placers,” by Murali et al., analyzes how the datasets of design metrics obtained from different stages of a 3D placement and routing flow affect a reinforced parameter tuning process. The tradeoff between desired power/performance/area (PPA) and training time for pseudo-3D and true-3D flows are also analyzed.
In addition to the 3D IC parameter tuning article, there are two more articles: multi-bit flip-flop clustering in 3D ICs; and substrate routing in package design. “GNN-Based Multi-Bit Flip-Flop Clustering and Post-Clustering Design Optimization for Energy-Efficient 3D ICs,” by Vanna-Iampikul et al., proposes a GNN-based algorithm to merge single-bit flip-flops into multi-bit flip-flops in an unsupervised manner, to reduce clock power in high-performance 3D ICs. The article “ILP-Based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package Design” proposes a new integer linear programming (ILP)-based router for wire-bonding in fine pitch ball grid array (FPBGA) packaging design. The published substrate-routing algorithm connects the bonding fingers of the chip's bonding wires with the assigned bump balls on the bottom of the ball grid array substrate.
The last article “CBDC-PUF: A Novel Physical Unclonable Function Design Framework Utilizing Configurable Butterfly Delay Chain Against Modeling Attack,” by Liu et al., proposes a secure hash function to insert non-linearities into a physical unclonable function (PUF) primitive for hardware security to produce many challenge/response pairs. It shows good results for randomness to prevent cloning, reliability, uniqueness, and resistance to modeling attacks, from the implementation on a Xilinx FPGA.
We would like to thank all the authors and reviewers for their tremendous contributions. This special issue would not be possible without their outstanding and timely work. Special thanks go to the TODAES editor-in-chief Professor X. Sharon Hu, and senior associate editor Professor Joerg Henkel, for their support of this special section, and Megan Shuler for her editorial efforts. We hope that the selected articles in this special issue will be valuable to the community.
Iris Hui-Ru Jiang
National Taiwan University
David Chinnery
Siemens Digital Industries Software
Gracieli Posser
Cadence Design Systems
Jens Lienig
Dresden University of Technology
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        cover image ACM Transactions on Design Automation of Electronic Systems
        ACM Transactions on Design Automation of Electronic Systems  Volume 28, Issue 5
        September 2023
        475 pages
        ISSN:1084-4309
        EISSN:1557-7309
        DOI:10.1145/3623508
        Issue’s Table of Contents

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        Association for Computing Machinery

        New York, NY, United States

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        Publication History

        Published: 09 September 2023
        Received: 01 June 2023
        Accepted: 28 May 2023
        Published in TODAES Volume 28, Issue 5

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