Stefan Stoyanov
ABSTRACT
This paper describes the architecture and development of a secure heterogeneous RISC-V system with protection dedicated core that provides hardware mechanisms for establishing root-of-trust, monitoring and controlling the execution of the rest of the cores in the system. The focus is on the security core which serves as control unit for the rest of the computational processors.
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Index Terms
- Secure Heterogeneous Architecture based on RISC-V and root-of-trust
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