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Special Session: Mitigating Side-channel Attacks through Circuit to Application Layer Approaches

Published: 19 January 2024 Publication History

Abstract

Side-Channel Attacks (SCAs), which are always considered a severe threat to the security of the cryptographic circuits, today can also be employed to extract IP secrets and neural network models. Hence, developing novel security solutions at different design levels is crucial. In this paper, we explore recent countermeasures at the circuit, algorithmic, and microarchitecture levels. First, we explain how Reconfigurable Field-Effect Transistor (RFET), as a beyond CMOS technology, enables us to provide both IP and data protection against SCAs at the circuit level. Second, we investigate an automated method for generating masked circuits as an algorithmic solution, and then we review machine learning-based SCA detection mechanisms at the microarchitecture level. Finally, we discuss emerging threats of SCAs from the industrial point of view.

References

[1]
Bilal Ali Ahmad. 2020. Real time detection of spectre and meltdown attacks using machine learning. arXiv preprint arXiv:2006.01442 (2020).
[2]
Gilles Barthe, Sonia Belaïd, François Dupressoir, Pierre-Alain Fouque, Benjamin Grégoire, Pierre-Yves Strub, and Rébecca Zucchini. 2016. Strong Non-Interference and Type-Directed Higher-Order Masking. In CCS. ACM, 116--129.
[3]
Lejla Batina, Shivam Bhasin, Dirmanto Jap, and Stjepan Picek. 2019. CSI NN: Reverse engineering of neural network architectures through electromagnetic side channel. In USENIX Security 19. 515--532.
[4]
Ali Galip Bayrak, Nikola Velickovic, Paolo Ienne, and Wayne Burleson. 2012. An architecture-independent instruction shuffler to protect against side-channel attacks. TACO 8, 4 (2012), 1--19.
[5]
Yu Bi, Kaveh Shamsi, Jiann-Shiun Yuan, Francois-Xavier Standaert, and Yier Jin. 2016. Leverage emerging technologies for DPA-resilient block cipher design. In DATE. IEEE, 1538--1543.
[6]
Gaëtan Cassiers, Benjamin Grégoire, Itamar Levi, and François-Xavier Standaert. 2021. Hardware Private Circuits: From Trivial Composition to Full Verification. IEEE TC (2021).
[7]
Gaëtan Cassiers and François-Xavier Standaert. 2020. Trivially and Efficiently Composing Masked Gadgets With Probe Isolating Non-Interference. IEEE TIFS 15 (2020), 2542--2555.
[8]
Suresh Chari, Charanjit S. Jutla, Josyula R. Rao, and Pankaj Rohatgi. 1999. Towards Sound Approaches to Counteract Power-Analysis Attacks. In CRYPTO 1999 (LNCS, Vol. 1666). Springer, 398--412.
[9]
Debayan Das, Shovan Maity, Saad Bin Nasir, Santosh Ghosh, Arijit Raychowdhury, and Shreyas Sen. 2017. High efficiency power side-channel attack immunity using noise injection in attenuated signature domain. In HOST. IEEE, 62--67.
[10]
Abhijitt Dhavlle, Houman Homayoun, and Sai Manoj Pudukotai Dinakarrao. 2022. CR-Spectre: Defense-aware ROP Injected Code-Reuse based Dynamic Spectre. In ACM/IEEE DATE.
[11]
Abhijitt Dhavlle, Raj Mehta, Setareh Rafatirad, Houman Homayoun, and Sai Manoj Pudukotai Dinakarrao. 2020. Entropy-Shield:Side-Channel Entropy Maximizationfor Timing-based Side-Channel Attacks. In ACM/EDAA/IEEE ISQED.
[12]
Abhijitt Dhavlle, Setareh Rafatirad, Khaled Khasawneh, Houman Homayoun, and Sai Manoj Pudukotai Dinakarrao. 2021. Imitating Functional Operations for Mitigating Side-Channel Leakage. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2021).
[13]
Anuj Dubey, Afzal Ahmad, Muhammad Adeel Pasha, Rosario Cammarota, and Aydin Aysu. 2022. Modulonet: Neural networks meet modular arithmetic for efficient hardware masking. IACR TCHES (2022), 506--556.
[14]
Anuj Dubey, Rosario Cammarota, and Aydin Aysu. 2020. BoMaNet: Boolean masking of an entire neural network. In ICCAD. 1--9.
[15]
Sebastian Faust, Vincent Grosso, Santos Merino Del Pozo, Clara Paglialonga, and François-Xavier Standaert. 2018. Composable Masking Schemes in the Presence of Physical Defaults & the Robust Probing Model. IACR TCHES 2018, 3 (2018), 89--120.
[16]
Tim Fritzmann, Michiel Van Beirendonck, Debapriya Basu Roy, Patrick Karl, Thomas Schamberger, Ingrid Verbauwhede, and Georg Sigl. 2022. Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography. IACR TCHES (2022), 414--460.
[17]
Giulio Galderisi, Christoph Beyer, Thomas Mikolajick, and Jens Trommer. 2023. Insights into the Temperature-Dependent Switching Behavior of Three-Gated Reconfigurable Field-Effect Transistors. physica status solidi (a) (2023).
[18]
Giulio Galderisi, Thomas Mikolajick, and Jens Trommer. 2022. Reconfigurable field effect transistors design solutions for delay-invariant logic gates. ESL 14, 2 (2022), 107--110.
[19]
Edouard Giacomin and Pierre-Emmanuel Gaillardon. 2018. Differential power analysis mitigation technique using three-independent-gate field effect transistors. In IFIP/IEEE VLSI-SoC. IEEE, 107--112.
[20]
Ian J Goodfellow, Jonathon Shlens, and Christian Szegedy. 2014. Explaining and harnessing adversarial examples. arXiv preprint arXiv:1412.6572 (2014).
[21]
Hannes Groß, Stefan Mangard, and Thomas Korak. 2016. Domain-Oriented Masking: Compact Masked Hardware Implementations with Arbitrary Protection Order. In TIS@CCS. ACM, 3.
[22]
Daniel Gruss, Clémentine Maurice, Klaus Wagner, and Stefan Mangard. 2016. Flush+Flush: A Fast and Stealthy Cache Attack. In Detection of Intrusions and Malware, and Vulnerability Assessment. Springer International Publishing, 279--299.
[23]
André Heinzig, Thomas Mikolajick, Jens Trommer, Daniel Grimm, and Walter M Weber. 2013. Dually active silicon nanowire transistors and circuits with equal electron and hole transport. Nano letters 13, 9 (2013), 4176--4181.
[24]
Gary Hilson. 2023. AI Must Be Secured at the Silicon Level. https://www.eetimes.com/ai-must-be-secured-at-the-silicon-level/
[25]
W.-M. Hu. 1992. Lattice scheduling and covert channels. In Proceedings 1992 IEEE Computer Society Symposium on Research in Security and Privacy. 52--61.
[26]
Xing Hu, Ling Liang, Shuangchen Li, Lei Deng, Pengfei Zuo, Yu Ji, Xinfeng Xie, Yufei Ding, Chang Liu, Timothy Sherwood, et al. 2020. Deepsniffer: A dnn model extraction framework based on learning architectural hints. In ASPLOS. 385--399.
[27]
Yunxiang Hu, Yuhao Liu, and Zhuovuan Liu. 2022. A survey on convolutional neural network accelerators: GPU, FPGA and ASIC. In ICCRD. IEEE, 100--107.
[28]
Yuval Ishai, Amit Sahai, and David A. Wagner. 2003. Private Circuits: Securing Hardware against Probing Attacks. In CRYPTO 2003 (LNCS, Vol. 2729). Springer, 463--481.
[29]
Monodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, and Saibal Mukhopadhyay. 2017. 8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator. In ISSCC. IEEE, 142--143.
[30]
Nima Kavand, Armin Darjani, Shubham Rai, and Akash Kumar. 2022. Securing Hardware through Reconfigurable Nano-Structures. In IEEE/ACM ICCAD. 1--7.
[31]
Nima Kavand, Armin Darjani, Shubham Rai, and Akash Kumar. 2023. Design of Energy-efficient RFET-based Exact and Approximate 4: 2 Compressors and Multipliers. IEEE TCAS-II (2023).
[32]
A. Kerckhoffs. 1883. La cryptographie militaire. Journal des Sciences Militaires (1883), 161--191.
[33]
Michael Keyser, Roman Gauchi, and Pierre-Emmanuel Gaillardon. 2022. An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge Computing. In IFIP/IEEE VLSI-SoC. IEEE, 1--6.
[34]
David Knichel and Amir Moradi. 2022. Low-Latency Hardware Private Circuits. In ACM CCS. ACM, 1799--1812.
[35]
David Knichel, Amir Moradi, Nicolai Müller, and Pascal Sasdrich. 2022. Automated Generation of Masked Hardware. IACR TCHES 2022, 1 (2022), 589--629.
[36]
David Knichel, Pascal Sasdrich, and Amir Moradi. 2020. SILVER - Statistical Independence and Leakage Verification. In ASIACRYPT 2020 (LNCS, Vol. 12491). Springer, 787--816.
[37]
David Knichel, Pascal Sasdrich, and Amir Moradi. 2022. Generic Hardware Private Circuits Towards Automated Generation of Composable Secure Gadgets. IACR TCHES 2022, 1 (2022), 323--344.
[38]
Paul Kocher, Jann Horn, Anders Fogh, Daniel Genkin, Daniel Gruss, Werner Haas, Mike Hamburg, Moritz Lipp, Stefan Mangard, Thomas Prescher, Michael Schwarz, and Yuval Yarom. 2019. Spectre Attacks: Exploiting Speculative Execution. In IEEE Symposium on Security and Privacy. 1--19.
[39]
Paul Kocher, Joshua Jaffe, and Benjamin Jun. 1999. Differential power analysis. In Advances in Cryptology---CRYPTO'99: 19th Annual International Cryptology Conference Santa Barbara, California, USA, August 15--19, 1999 Proceedings 19. Springer, 388--397.
[40]
Paul C Kocher. 1996. Timing attacks on implementations of Diffie-Hellman, RSA, DSS, and other systems. In Advances in Cryptology---CRYPTO'96: 16th Annual International Cryptology Conference Santa Barbara, California, USA August 18--22, 1996 Proceedings 16. Springer, 104--113.
[41]
Congmiao Li and Jean-Luc Gaudiot. 2018. Online Detection of Spectre Attacks Using Microarchitectural Traces from Performance Counters. In SBAC-PAD. 25--28.
[42]
Moritz Lipp, Michael Schwarz, Daniel Gruss, Thomas Prescher, Werner Haas, Anders Fogh, Jann Horn, Stefan Mangard, Paul Kocher, Daniel Genkin, Yuval Yarom, and Mike Hamburg. 2018. Meltdown: Reading Kernel Memory from User Space. In USENIX Security. USENIX Association, Baltimore, MD, 973--990.
[43]
Steffen Märcker, Michael Raitza, Shubham Rai, Giulio Galderisi, Thomas Mikolajick, Jens Trommer, and Akash Kumar. 2023. Formal Analysis of Camouflaged Reconfigurable Circuits. In NEWCAS. 1--4.
[44]
Maria Méndez Real and Ruben Salvador. 2021. Physical side-channel attacks on embedded neural networks: A survey. Applied Sciences 11, 15 (2021), 6790.
[45]
T Mikolajick, G Galderisi, S Rai, M Simon, R Böckle, M Sistani, C Cakirlar, N Bhattacharjee, T Mauersberger, A Heinzig, et al. 2022. Reconfigurable field effect transistors: A technology enablers perspective. Solid-State Electronics (2022), 108381.
[46]
T Mikolajick, G Galderisi, M Simon, S Rai, A Kumar, A Heinzig, WM Weber, and J Trommer. 2021. 20 Years of reconfigurable field-effect transistors: From concepts to future applications. Solid-State Electronics 186 (2021), 108036.
[47]
Kamyar Mohajerani, Luke Beckwith, Abubakr Abdulgadir, Eduardo Ferrufino, Jens-Peter Kaps, and Kris Gaj. 2023. SCA Evaluation and Benchmarking of Finalists in the NIST Lightweight Cryptography Standardization Process. Cryptology ePrint Archive, Paper 2023/484.
[48]
Nicolai Müller and Amir Moradi. 2022. PROLEAD A Probing-Based Hardware Leakage Detection Tool. IACR TCHES 2022, 4 (2022), 311--348.
[49]
Onur Mutlu, Saugata Ghose, Juan Gómez-Luna, and Rachata Ausavarungnirun. 2022. A modern primer on processing in memory. In Emerging Computing: From Devices to Systems: Looking Beyond Moore and Von Neumann. Springer, 171--243.
[50]
Svetla Nikova, Christian Rechberger, and Vincent Rijmen. 2006. Threshold Implementations Against Side-Channel Attacks and Glitches. In ICICS 2006 (LNCS, Vol. 4307). Springer, 529--545.
[51]
Dag Arne Osvik, Adi Shamir, and Eran Tromer. 2006. Cache attacks and counter-measures: the case of AES. In CT-RSA. Springer, 1--20.
[52]
Zhixin Pan and Prabhat Mishra. 2021. Automated Detection of Spectre and Meltdown Attacks Using Explainable Machine Learning. In IEEE HOST. 24--34.
[53]
Biagio Peccerillo, Mirco Mannino, Andrea Mondelli, and Sandro Bartolini. 2022. A survey on hardware accelerators: Taxonomy, trends, challenges, and perspectives. Journal of Systems Architecture 129 (2022), 102561.
[54]
Shubham Rai, Jens Trommer, Michael Raitza, Thomas Mikolajick, Walter M Weber, and Akash Kumar. 2018. Designing efficient circuits based on runtime-reconfigurable field-effect transistors. IEEE TVLSI 27, 3 (2018), 560--572.
[55]
Tobias Schneider, Amir Moradi, and Tim Güneysu. 2015. Arithmetic Addition over Boolean Masking: Towards First-and Second-Order Resistance in Hardware. In ACNS. Springer, 559--578.
[56]
Adi Shamir. 1979. How to Share a Secret. Commun. ACM 22, 11 (1979), 612--613.
[57]
Mohammad Mehdi Sharifi, Ramin Rajaei, Patsy Cadareanu, Pierre-Emmanuel Gaillardon, Yier Jin, Michael T Niemier, and Xiaobo Sharon Hu. 2020. A Novel TIGFET-based DFF Design for Improved Resilience to Power Side-Channel Attacks. In DATE. 1253--1258.
[58]
Zhongkai Tong, Ziyuan Zhu, Zhanpeng Wang, Limin Wang, Yusha Zhang, and Yuxin Liu. 2020. Cache side-channel attacks detection based on machine learning. In TrustCom. 919--926.
[59]
Han Wang, Hossein Sayadi, Avesta Sasan, Setareh Rafatirad, Tinoosh Mohsenin, and Houman Homayoun. 2020. Comprehensive evaluation of machine learning countermeasures for detecting microarchitectural side-channel attacks. In GLSVLSI. 181--186.
[60]
Ziyu Wang, Fan-hsuan Meng, Yongmo Park, Jason K Eshraghian, and Wei D Lu. 2023. Side-channel attack analysis on in-memory computing architectures. TETC (2023).
[61]
Peng Wu, Dayane Reis, Xiaobo Sharon Hu, and Joerg Appenzeller. 2021. Two-dimensional transistors with reconfigurable polarities for secure circuits. NATURE electronics 4, 1 (2021), 45--53.
[62]
Yuval Yarom and Katrina Falkner. 2014. FLUSH+RELOAD: A High Resolution, Low Noise, L3 Cache Side-Channel Attack. In USENIX security. 719--732.
[63]
Kota Yoshida, Takaya Kubota, Mitsuru Shiozaki, and Takeshi Fujino. [n. d.]. Model-extraction attack against FPGA-DNN accelerator utilizing correlation electromagnetic analysis. In FCCM.
[64]
Jian Zhang, Michele De Marchi, Davide Sacchetto, Pierre-Emmanuel Gaillardon, Yusuf Leblebici, and Giovanni De Micheli. 2014. Polarity-controllable silicon nanowire transistors with dual threshold voltages. IEEE Transactions on Electron Devices 61, 11 (2014), 3654--3660.

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        cover image ACM Conferences
        CODES/ISSS '23 Companion: Proceedings of the 2023 International Conference on Hardware/Software Codesign and System Synthesis
        September 2023
        61 pages
        ISBN:9798400702891
        DOI:10.1145/3607888
        Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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        Published: 19 January 2024

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        Author Tags

        1. hardware security
        2. side-channel analysis
        3. emerging technology
        4. masking

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