Leon Werner
ABSTRACT
The increasing number of cores per processor requires powerful on-chip networks to take full advantage of the processor performance. However, the wide variety of available networks with possibly varying communication latencies, makes a realistic performance evaluation very difficult. Of course, there are already many publications and tools available for network evaluation, but most of them are limited to a few specific architectures.
This paper presents a framework for the performance evaluation of networks-on-chip architectures implemented in SystemVerilog. The framework uses Verilator to provide cycle- and gate-accurate simulation of network behavior under load. Different traffic generation patterns allow a variety of network performance statistics to be determined. The number of cycles each message spends between creation and reception is recorded during the simulation and then combined with timing estimates from XILINX Vivado to calculate an expected network bandwidth. Other performance data, such as the maximum I/O capacity of a single network node, can also be obtained from the message patterns provided by the traffic generator. To demonstrate the use of our framework, we compare and evaluate the open source 2D mesh network RaveNoc with a blocking Ω-network and a nonblocking fat tree network.
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Index Terms
- Network-On-Chip Performance Evaluation by Synchronous Circuit Simulation
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