research-article

Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology

Authors:

Pushkar Praveen,

R. K. SinghAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems, Volume 28, Issue 6

Article No.: 105, Pages 1 - 29

https://doi.org/10.1145/3616538

Published: 28 October 2023 Publication History

Abstract

Power dissipation is considered one of the important issues in low power Very-large-scale integration (VLSI) circuit design and is related to the threshold voltage. Generally, the sub-threshold leakage current and the leakage power dissipation are increased by reducing the threshold voltage. The overall performance of the circuit completely depends on this leakage power dissipation because this leakage and power consumption causes the components that are functioning by the battery for a long period to be washed-out rapidly. In this research, the reversible logic gate-based 9T static random access memory (SRAM) is designed in 14nm FinFET technology to reduce leakage power consumption in memory related applications. The Schmitt-trigger (ST)-based 9T SRAM cell is designed to attain high read-write stability and low power consumption using a single bit line structure. The reversible logic gates of Feynman (FG) and Fredkin gate (FRG) are combined to develop a row and column decoder in an SRAM design to diminish the leakage power. Moreover, the transistor stacking effect is applied to the proposed memory design to reduce the leakage power in active mode. The proposed reversible logic and transistor stacking based SRAM design is implemented in Tanner EDA Tool version 16.0. It also performs both read and write operations using the proposed circuit. The performance measures of read access time (RAT), write access time (WAT), read, write, and static power by varying supply voltage and temperature, delay and stability analysis (read/write static noise margin) are examined and compared with existing SRAM designs.

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Cited By

Srivastav ATripathi STiwari UMandal S(2024)Comprehensive Study of Low-Power SRAM Design TopologiesRecent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering)10.2174/012352096527586123102706081717:9(849-858)Online publication date: Nov-2024
https://doi.org/10.2174/0123520965275861231027060817
Soni LPandey N(2024)A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM CellACM Transactions on Design Automation of Electronic Systems10.1145/365367529:4(1-13)Online publication date: 9-Jul-2024
https://dl.acm.org/doi/10.1145/3653675
Tripathi ADahiya AMittal P(2024)A low-power single ended half-select free 7 T SRAM cell with improved write margin at 32 nm technology nodePhysica Scripta10.1088/1402-4896/ad96f3100:1(015015)Online publication date: 6-Dec-2024
https://doi.org/10.1088/1402-4896/ad96f3
Show More Cited By

Index Terms

Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology
1. General and reference
  1. Cross-computing tools and techniques
    1. Validation

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 28, Issue 6

November 2023

404 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3627977

Editor:
Hu X. Sharon
University of Notre Dame, USA

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 28 October 2023

Online AM: 24 August 2023

Accepted: 29 June 2023

Revised: 26 June 2023

Received: 11 June 2022

Published in TODAES Volume 28, Issue 6

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Cited By

Srivastav ATripathi STiwari UMandal S(2024)Comprehensive Study of Low-Power SRAM Design TopologiesRecent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering)10.2174/012352096527586123102706081717:9(849-858)Online publication date: Nov-2024
https://doi.org/10.2174/0123520965275861231027060817
Soni LPandey N(2024)A Single Bitline Highly Stable, Low Power With High Speed Half-Select Disturb Free 11T SRAM CellACM Transactions on Design Automation of Electronic Systems10.1145/365367529:4(1-13)Online publication date: 9-Jul-2024
https://dl.acm.org/doi/10.1145/3653675
Tripathi ADahiya AMittal P(2024)A low-power single ended half-select free 7 T SRAM cell with improved write margin at 32 nm technology nodePhysica Scripta10.1088/1402-4896/ad96f3100:1(015015)Online publication date: 6-Dec-2024
https://doi.org/10.1088/1402-4896/ad96f3
Praveen PSingh R(2024)Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technologyInternational Journal of Circuit Theory and Applications10.1002/cta.4143Online publication date: 27-Jun-2024
https://doi.org/10.1002/cta.4143

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