Julian Oppermann
ABSTRACT
In the RISC-V ecosystem, custom instruction set architecture extensions (ISAX) are an energy-efficient and cost-effective way to accelerate modern embedded workloads. However, exploring different combinations of base cores and ISAXes for a specific application requires automation and a level of portability across microarchitectures that is not provided by existing approaches.
To that end, we present an end-to-end flow for ISAX specification, generation, and integration into a number of host cores having a range of different microarchitectures. For ISAX specification, we propose CoreDSL, a novel behavioral architecture description language that is concise, easy to learn, and open source. Hardware generation is handled by Longnail, a domain-specific high-level synthesis tool that compiles CoreDSL specifications into hardware modules compatible with the recently introduced SCAIE-V extension interface, which we rely on for automatic integration into the host cores.
We demonstrate our tooling by generating ISAXes using a mix of features, including complex multi-cycle computations, memory accesses, branch instructions, custom registers, and decoupled execution across four embedded cores and evaluate the quality of results on a 22nm ASIC process.
- A FPGA friendly 32 bit RISC-V CPU implementation. https://github.com/SpinalHDL/VexRiscv.Google Scholar
- Language engineering for everyone. https://eclipse.dev/Xtext/.Google Scholar
- Mirror of the now discontinued ORCA RISC-V processor from Vector-Blox. https://github.com/cahz/orca.Google Scholar
- PicoRV32 - A Size-Optimized RISC-V CPU. https://github.com/YosysHQ/picorv32.Google Scholar
- RISC-V CPU, simple 3-stage pipeline, for low-end applications. https://github.com/bluespec/Piccolo.Google Scholar
- The OpenHW Group CORE-V-XIF interface. https://docs.openhwgroup.org/projects/openhw-group-core-v-xif/en/latest/.Google Scholar
- Hela Belhadj Amor, Carolynn Bernier, and Zdenek Prikryl. A RISC-V ISA extension for ultra-low power iot wireless signal processing. IEEE Trans. Computers, 71(4):766--778, 2022.Google ScholarCross Ref
- Andes. Andes custom extension. http://www.andestech.com/en/products-solutions/andes-custom-extension/.Google Scholar
- Krste Asanović, Rimas Avizienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Daniel Palmer Dabbelt, John R. Hauser, Adam M. Izraelevitz, Sagar Karandikar, Benjamin Keller, Donggyu Kim, Jack Koenig, Krste Asanović, Rimas Avizienis, Palmer Dabbelt, Benjamin Keller, Yunsup Lee, Eric Love, Martin Maas, Albert Magyar, Howard Mao, Miquel Moretó, Albert J. Ou, David A. Patterson, Brian C. Richards, Colin Schmidt, Stephen Twigg, Huy D. Vo, and Andrew Waterman. The rocket chip generator. 2016.Google Scholar
- Paul Palomero Bernardo, Patrick Schmid, Oliver Bringmann, Mohammed Iftekhar, Babak Sadiye, Wolfgang Müller, Andreas Koch, Eyck Jentzsch, Axel Sauer, Ingo Feldner, and Wolfgang Ecker. A scalable risc-v hardware platform for intelligent sensor processing. In Design, Automation & Test in Europe Conference & Exhibition, DATE 2024, 2024.Google Scholar
- Abhishek Bit. 64-Bit Custom Math ISA in Configurable 32-Bit RISC Processor. In Amit Kumar, Marcin Paprzycki, and Vinit Kumar Gunjan, editors, ICDSMLA 2019, volume 601, pages 564--575. Springer Singapore, Singapore, 2020. Series Title: Lecture Notes in Electrical Engineering.Google Scholar
- Matheus Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, and Luca Benini. Spatz: A compact vector processing unit for high-performance and energy-efficient shared-l1 clusters. In 2022 IEEE/ACM International Conference On Computer Aided Design (ICCAD), pages 1--9, 2022.Google Scholar
- Hao Cheng, Johann Großschädl, Ben Marshall, Dan Page, and Thinh Hung Pham. RISC-V instruction set extensions for lightweight symmetric cryptography. IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023(1):193--237, 2023.Google Scholar
- CIRCT. Circuit IR Compilers and Tools. https://circt.llvm.org.Google Scholar
- CIRCT. 'comb' Dialect. https://circt.llvm.org/docs/Dialects/Comb/.Google Scholar
- CIRCT. 'hw' Dialect. https://circt.llvm.org/docs/Dialects/HW/.Google Scholar
- CIRCT. 'hwarith' Dialect. https://circt.llvm.org/docs/Dialects/HWArith/.Google Scholar
- CIRCT. 'seq' Dialect. https://circt.llvm.org/docs/Dialects/Seq/.Google Scholar
- CIRCT. Static scheduling infrastructure. https://circt.llvm.org/docs/Scheduling/.Google Scholar
- CIRCT. 'sv' Dialect. https://circt.llvm.org/docs/Dialects/SV/.Google Scholar
- Codasip. Mythic case study. https://codasip.com/wp-content/uploads/2021/03/Codasip_case-study_Mythic.pdf.Google Scholar
- Codasip. What is CodAL? https://codasip.com/2021/02/26/what-is-codal/.Google Scholar
- Mihaela Damian, Julian Oppermann, Christoph Spang, and Andreas Koch. SCAIE-V: an open-source scalable interface for ISA extensions for RISC-V processors. In Rob Oshana, editor, DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 -14, 2022, pages 169--174. ACM, 2022.Google ScholarDigital Library
- Giovanni De Micheli. Synthesis and optimization of digital circuits. McGraw-Hill series in electrical and computer engineering. McGraw-Hill, New York, 1994.Google ScholarDigital Library
- Colin Drewes. Rethinking CPU-FPGA Interfaces: A Reconfigurable RISC-V Co-Processor. https://colindrewes.com/projects/GPCP.pdf.Google Scholar
- Wolfgang Ecker, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grüttner, Paul Palomero Bernardo, Oliver Bringmann, Mihaela Damian, Julian Oppermann, Andreas Koch, Jörg Bormann, Johannes Partzsch, Christian Mayr, and Wolfgang Kunz. The scale4edge RISC-V ecosystem. In Cristiana Bolchini, Ingrid Verbauwhede, and Ioana Vatajelu, editors, 2022 Design, Automation & Test in Europe Conference & Exhibition, DATE 2022, Antwerp, Belgium, March 14-23, 2022, pages 808--813. IEEE, 2022.Google ScholarCross Ref
- Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, and Luca Benini. Near-threshold RISC-V core with DSP extensions for scalable iot endpoint devices. IEEE Trans. Very Large Scale Integr. Syst., 25(10):2700--2713, 2017.Google ScholarDigital Library
- Tiago Gomes, Pedro Sousa, Miguel Silva, Mongkol Ekpanyapong, and Sandro Pinto. Fac-v: An fpga-based aes coprocessor for risc-v. Journal of Low Power Electronics and Applications, 12(4), 2022.Google ScholarCross Ref
- Ricardo E. Gonzalez. Xtensa: A configurable and extensible processor. IEEE Micro, 20(2):60--70, 2000.Google ScholarDigital Library
- Google. Or-tools. https://developers.google.com/optimization.Google Scholar
- Jan Gray. Draft Proposed RISC-V Composable Custom Extensions Specification, v. 0.92.231111. https://github.com/grayresearch/CX/blob/main/spec/spec.pdf, 2023.Google Scholar
- Brad Green, Dillon Todd, Jon C. Calhoun, and Melissa C. Smith. Tigra: A tightly integrated generic risc-v accelerator interface. In 2021 IEEE International Conference on Cluster Computing (CLUSTER), pages 779--782, 2021.Google ScholarCross Ref
- Carsten Heinz, Yannick Lavan, Jaco A. Hofmann, and Andreas Koch. A catalog and in-hardware evaluation of open-source drop-in compatible RISC-V softcore processors. In David Andrews, René Cumplido, Claudia Feregrino, and Marco Platzner, editors, 2019 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2019, Cancun, Mexico, December 9-11, 2019, pages 1--8. IEEE, 2019.Google ScholarCross Ref
- Bewoayia Kebianyor Jan Schlamelcher, Thomas Goodfellow and Kim Grüttner. Extending clang/llvm with custom instruction using tablegen - an experience report. In 2024 Methods and Description Languages for Modelling and Verification of Circuits and Systems (MBMV). VDE/IEEE, 2024.Google Scholar
- Ryan Kabrick, John D. Leidel, and David Donofrio. Toward HDL extensions for rapid AI/ML accelerator generation. In 2021 IEEE High Performance Extreme Computing Conference, HPEC 2021, Waltham, MA, USA, September 20-24, 2021, pages 1--6. IEEE, 2021.Google ScholarCross Ref
- Johannes Kappes, Robert Kunzelmann, Karsten Emrich, Conrad Foik, Daniel Mueller-Gritschneder, and Wolfgang Ecker. Effective processor model generation from instruction set simulator to hardware design. In 2023 IEEE Nordic Circuits and Systems Conference (NorCAS). IEEE, 2023.Google ScholarCross Ref
- Stanislaw Kaushanski and Eyck Jentzsch. Automated cross-level verification flow of a highly configurable risc-v core family with custom instructions. In RISC-V Summit Europe, 2023.Google Scholar
- Chris Lattner, Mehdi Amini, Uday Bondhugula, Albert Cohen, Andy Davis, Jacques A. Pienaar, River Riddle, Tatiana Shpeisman, Nicolas Vasilache, and Oleksandr Zinenko. MLIR: scaling compiler infrastructure for domain specific computation. In Jae W. Lee, Mary Lou Soffa, and Ayal Zaks, editors, IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2021, Seoul, South Korea, February 27 - March 3, 2021, pages 2--14. IEEE, 2021.Google Scholar
- John D. Leidel, David Donofrio, and Frank Conlon. Stonecutter: a very high level instruction set design language. In Maurizio Palesi, Gianluca Palermo, Catherine Graves, and Eishi Arima, editors, Proceedings of the 17th ACM International Conference on Computing Frontiers, CF 2020, Catania, Sicily, Italy, May 11-13, 2020, pages 233--236. ACM, 2020.Google Scholar
- John D. Leidel, Ryan Kabrick, and David Donofrio. Toward an automated hardware pipelining LLVM pass infrastructure. In 7th IEEE/ACM Workshop on the LLVM Compiler Infrastructure in HPC, LLVM-HPC@SC 2021, St. Louis, MO, USA, November 14, 2021, pages 39--49. IEEE, 2021.Google ScholarCross Ref
- Robin Lougee-Heimer. The common optimization interface for operations research: Promoting open-source software in the operations research community. IBM Journal of Research and Development, 47(1):57--66, 2003.Google ScholarDigital Library
- Eric Matthews and Lesley Shannon. TAIGA: A new RISC-V soft-processor framework enabling high performance CPU architectural features. In 2017 27th International Conference on Field Programmable Logic and Applications (FPL), pages 1--4, 2017.Google ScholarCross Ref
- Prabhat Mishra and Nikil Dutt. Chapter 1 - Introduction to Architecture Description Languages. In Prabhat Mishra and Nikil Dutt, editors, Processor Description Languages, volume 1 of Systems on Silicon, pages 1--12. Morgan Kaufmann, Burlington, 2008. ISSN: 18759661.Google Scholar
- Prabhat Mishra and Aviral Shrivastava. Chapter 2 - ADL-driven Methodologies for Design Automation of Embedded Processors. In Prabhat Mishra and Nikil Dutt, editors, Processor Description Languages, volume 1 of Systems on Silicon, pages 13--33. Morgan Kaufmann, Burlington, 2008. ISSN: 18759661.Google Scholar
- MLIR. 'func' Dialect. https://mlir.llvm.org/docs/Dialects/Func/.Google Scholar
- MLIR. 'memref' Dialect. https://mlir.llvm.org/docs/Dialects/MemRef/.Google Scholar
- MLIR. 'scf' Dialect. https://mlir.llvm.org/docs/Dialects/SCFDialect/.Google Scholar
- Khai-Duy Nguyen, Tuan-Kiet Dang, Trong-Thuc Hoang, Quynh Nguyen Quang Nhu, and Cong-Kha Pham. A cordic-based trigonometric hardware accelerator with custom instruction in 32-bit RISC-V system-on-chip. In IEEE Hot Chips 33 Symposium, HCS 2021, Palo Alto, CA, USA, August 22-24, 2021, pages 1--13. IEEE, 2021.Google ScholarCross Ref
- Julian Oppermann, Lukas Sommer, Lukas Weber, Melanie Reuter-Oppermann, Andreas Koch, and Oliver Sinnen. Skycastle: A resource-aware multi-loop scheduler for high-level synthesis. In International Conference on Field-Programmable Technology, FPT 2019, Tianjin, China, December 9-13, 2019, pages 36--44. IEEE, 2019.Google ScholarCross Ref
- Johan Van Praet, Dirk Lanneer, Werner Geurts, and Gert Goossens. Chapter 4 - nML: A Structural Processor Modeling Language for Retargetable Compilation and ASIP Design. In Prabhat Mishra and Nikil Dutt, editors, Processor Description Languages, volume 1 of Systems on Silicon, pages 65--93. Morgan Kaufmann, Burlington, 2008. ISSN: 18759661.Google Scholar
- Himanshu A. Sanghavi and Nupur B. Andrews. Chapter 8 - TIE: An ADL for Designing Application-specific Instruction Set Extensions. In Prabhat Mishra and Nikil Dutt, editors, Processor Description Languages, volume 1 of Systems on Silicon, pages 183--216. Morgan Kaufmann, Burlington, 2008. ISSN: 18759661.Google Scholar
- Alexey Shchekin and Ettore Giliberti. Compact CORDIC accelerator implementation for embedded RISC-V core. In RISC-V Summit Europe 2023.Google Scholar
- Cadence Design Systems. TIE Language - The Fast Path to High-Performance Embedded SoC Processing. https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/ip/tensilica-ip/tip-tie-wp.pdf, 2016.Google Scholar
- Andrew Waterman and Krste Asanovic. The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA. https://riscv.org/technical/specifications, 2019.Google Scholar
- F. Zaruba and L. Benini. The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(11):2629--2640, Nov 2019.Google ScholarDigital Library
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