Jai-Ming Lin
ABSTRACT
Since the multilevel framework with the analytical approach has been proven as a promising method to handle the very-large-scale integration (VLSI) placement problem, this paper presents two techniques including a pin-connectivity-aware cluster score function and identification of expected object distribution ranges to further improve the coarsening and refinement stages of this framework. Moreover, we extend the proposed analytical placement method to consider timing in order to speed up design convergence. To optimize timing without increasing wirelength, our approach only increases the weights of timing-critical nets, where the weight of a net is estimated according to the associated timing slack and degree. Besides, we propose a new equation to update net weights based on their historical values to maintain the stability of the net-based timing-driven placement approach. Experimental results demonstrate that the proposed analytical placement approach with new techniques can actually improve wirelength of the classic approach. Moreover, our TDP can get much better WNS and TNS than the previous timing-driven placers such as DREAMPlace4.0 and Differentiable TDP.
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Index Terms
- Timing-Driven Analytical Placement According to Expected Cell Distribution Range
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