Wang-Tyng Lay
ABSTRACT
With the advancements in 2.5/3D fabrication offered by Foundry Technologies for unleashing computing power, EDA tools must adapt and take a direction to be more integrated and IC centric for multi-chiplet system design. 3D stacking introduces extra design and analysis requirements like full system planning, power, thermal analysis, cross-die STA and inter-die physical verification which have to be taken into account early during planning and implementation. In this paper, Cadence presents its technology that proactively looks ahead through integrated early analysis and addresses all aspects of 3D-IC design comprehensively from system planning, implementation, analysis and system level signoff capabilities.
- TSMC 3DFabric https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/3DFabric.htm#techGoogle Scholar
- Samsung Foundry - Advanced Package https://semiconductor.samsung.com/foundry/advanced-package/Google Scholar
- Intel Foundry -- Chiplets https://www.intel.com/content/www/us/en/foundry/chiplets.htmlGoogle Scholar
- Cadence 3D-IC Design Solution https://www.cadence.com/en_US/home/solutions/3dic-design-solutions.htmlGoogle Scholar
- 3Dblox Standard https://3dblox.org/Google Scholar
- TSMC EDA Alliance --3DFabric EDA Tool Certification https://www.tsmc.com/english/dedicatedFoundry/oip/eda_allianceGoogle Scholar
Index Terms
- Unified 3D-IC Multi-Chiplet System Design Solution
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