ABSTRACT
Thermal Challenge from modeling heterogeneous 2.5/3D IC-package is important for several reasons. Designing a large high power device, e.g. a AI or HPC processor without considering how to get the heat out is likely to lead to problems later on, resulting in a sub-optimal packaging solution from cost, size, weight and performance perspectives. Thermal simulation combines with physical verification. The benefits are enablement for automatic extraction, power map generation and simulation of the complete 3D IC assembly, viewing thermal map, and addressing hotspot. Make the IC design flow aware temperature and hotspot at the early design stage.
- https://resources.sw.siemens.com/hu-HU/video-simplified-physical-verification-of-3dics-through-3dbloxtmGoogle Scholar
- https://blogs.sw.siemens.com/semiconductor-packaging/2022/07/07/the-beginners-guide-to-3d-ic/Google Scholar
- https://newsroom.sw.siemens.com/en-US/siemens-tsmc-oip-22/Google Scholar
- P. Vivet, Y. Thonnart, R. Lemaire, C. Santos, E. Beigne, C. Bernard, F. Darve, D. Lattard, I. Miro-Panades, D. Dutoit, F. Clermidy, S. Cheramy, H. Sheibanyrad, F. Petrot, E. Flamand, J. Michailos, A. Arriordaz, L. Wang and J. Schloeffel, A 4x4x2 Homogeneous Scalable 3D Network-on-Chip Circuit with 326 MFlit/s 0.66 pJ/bit Robust and Fault Tolerant Asynchronous 3D links", IEEE Journal of Solid-State Circuits (Volume: 52, Issue: 1, January 2017).Google ScholarCross Ref
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