Challenges in Floorplanning and Macro Placement for Modern SoCs

Modern System-on-Chips (SoCs), such as smartphone microprocessors, are composed of billions of transistors existing in various subsystems. These subsystems can include Central Processing Units (CPUs), Graphics Processing Units (GPUs), Neural Processing Units (NPUs), Image Signal Processors (ISPs), Digital Signal Processors (DSPs), communication modems, memory controllers, and many others. For efficient Electronic Design Automation (EDA) tasks, such as those involving logic synthesis, placement, clock tree synthesis (CTS), and/or routing, these subsystems are typically broken down into smaller, more manageable circuit blocks, or circuit partitions. This subdivision strategy is crucial for keeping design times within reasonable limits.

During the top-level floorplanning phase of chip design, the dimensions, interconnect ports, and physical locations of circuit partitions are defined; the physical boundaries of these partitions are commonly designed as rectilinear shapes rather than rectangles. Partitions that are excessively large can lead to inefficient use of chip area, higher power consumption, and higher production costs. Conversely, undersized partitions can hinder subsequent physical design processes, potentially causing delays in the overall chip design schedule. Furthermore, a poor floorplan can lead to longer wire lengths and can increase feedthrough net counts in partitions, adversely affecting power, performance, and area (PPA).

In practice, the top-level floorplanning phase of chip design can involve multiple iterations of its processes. An initial iteration typically involves estimating the approximate area of each circuit partition based on various factors, such as the dimensions of macros (including SRAM macros), the number of standard cell instances, and the standard cell utilization rate, which can be projected based on the data from previous designs. These preliminary estimates are crucial for defining the initial shapes, dimensions, interconnect ports, and physical locations of the partitions. Subsequently, the downstream design processes can advance either to partition-level physical design (which includes macro placement, standard cell placement, CTS, routing, etc.) or to physical-aware logic synthesis, which uses the defined layout data to more precisely assess layout-induced effects and produce more accurate gate-level netlists.

Once the dimensions and interconnect locations of circuit partitions are defined, macro placement, which is usually followed by standard cell placement and routing processes, can be conducted. After performing these processes, PPA results may indicate that certain partitions require size adjustments due to being too small, whereas others may be identified as candidates for area reduction. Such alterations in the circuit partition areas necessitate modifications to the top-level floorplan. Furthermore, in subsequent iterations of floorplanning, certain elements (such as feedthrough nets/ports) may be added into and/or removed from partitions, prompting a reevaluation of the physical implementation feasibility for these partitions; the reevaluation stage may involve additional macro placement, cell placement, and routing activities.

Macro placement is crucial in physical design as its outcomes can substantially influence standard cell placement, CTS, routing, circuit timing, and even power consumption. However, at advanced technology nodes, macro placement outcomes produced by commercial EDA tools and reinforcement learning (RL)-based tools often require human modifications prior to practical use, which in part owing to complex design rules associated with advanced technology nodes, although these tools can rapidly generate results. Additionally, it has been observed that suboptimal macro placement can lead to issues such as IR drop and increased dynamic/static power consumption. However, these issues, which may be checked more accurately in later stages of a design flow, are frequently not addressed in a typical macro placement process. In modern SoCs, moreover, it is very common that a circuit partition contains multiple power domains. Performing macro placement on this type of circuit partition may require domain floorplanning prior to placing macros and standard cell instances within their respective power domain regions.

As described previously, the floorplanning and the macro placement are often interrelated. Early iterations of floorplanning may not achieve the best configurations for partitions in terms of PPA, leading to additional iterations in the design flow. Also, the macro placement process, along with subsequent cell placement and routing tasks, can serve as a critical and potentially fast evaluation step to assess each partition's physical implementation feasibility, thereby driving continuous refinements in the floorplan. This iterative methodology is crucial in achieving a more refined and optimized chip design, which is especially critical at advanced technology nodes where wafer costs are significantly high.

In designing modern SoCs, the importance of performing high-quality floorplanning and high-quality macro placement cannot be overemphasized. Specifically, the floorplanning and the macro placement challenges encountered in the industry, and the obstacles preventing complete automation of these processes need to be re-examined. With ongoing advancements in EDA and AI/ML technologies, such as the application of reinforcement learning (RL) in tuning design flow parameters, coupled with enhanced computational power, we anticipate a substantial improvement and/or potential automation in the iterative aspects of these design processes. Such advancements will not only alleviate the workload of engineers but also enhance the overall quality of results (QoR) in chip designs.