My Fifteen Year Journey of Deploying FPGA Accelerated Solutions

While FPGAs have been investigated for accelerating computing workloads in academia for many decades, industry started adopting FPGAs as an accelerator only in the last decade, but even those deployments have been fairly limited. This talk describes my journey over 15 years of building and deploying FPGA accelerated solutions. In my career, I have led the integration of FPGAs with CPUs in a variety of ways, each seeking the right mix of efficiency, capability, and cost. The first phase of the journey begins at Intel in 2008 in building the first solutions with socketed FPGAs attached to Xeon CPUs using FSB and QPI coherent buses. These coherently attached FPGAs enabled various new use cases beyond the PCIe attached FPGA accelerators leading to projections of wide scale deployment of FPGAs in the data center. Intel's acquisition of Altera in 2015 kicked off the second phase where we integrated a FPGA die with a Xeon die to produce a multi-chip package that dropped into a Xeon socket. This was introduced in the market targeting communication workloads. We formed Megh Computing in 2017 to enable a FPGA accelerated edge platform for analytics workloads in the enterprise which resulted in solutions for video surveillance. The talk will discuss the various challenges and breakthroughs in deploying FPGA accelerators from the edge to the datacenter, where I see the market headed in the near future and identify promising directions and tough problems the FPGA research community need to tackle to realize the potential of reconfigurable computing.