Anchit Arun
ABSTRACT
In most implementations of digital circuitry, multiplication requires the highest latency and computational complexity. Vedic calculations are an ancient system of mathematics that involves mathematical computations to ascertain the multiplication in faster implementation. In this paper, Urdhva Tiryagbhyam Sutra inspired Vedic Multiplier algorithm is used for multiplication rather than conventional multiplication, enabling simple and quick computation with limited hardware resources. 99.329% fault coverage was achieved using the ATALANTA tool, and the results after incorporating Automatic Test Pattern Generation (ATPG) are encouraging. The synthesis and functional verification of the proposed arithmetic circuit are carried out in Quartus Prime and the ModelSim 20.1 Intel simulator, respectively. Additionally, the latency and power consumption obtained are 7.89 ns and 0.164 nW, respectively, which is significantly less than the current designs. By using a fault collapsing technique with no aborted faults, 298 collapsed faults, 2 backtrackings, 33 test patterns before compactions, and a minimum of 20 test patterns after compactions, the design testing time is reduced.
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Index Terms
- Power and Delay Efficient Hardware Implementation with ATPG for Vedic Multiplier Using Urdhva Tiryagbhyam Sutra
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