ABSTRACT
New non-volatile memory technologies show great promise for extending the memory hierarchy, but have limited endurance that needs to be mitigated toward their reliable use closer to the processor. Wear leveling is a common technique for prolonging the life of endurance-limited memory, where existing wear-leveling approaches either employ costly full-indirection mapping between logical and physical addresses, or choose simple mappings that cannot cope with extremely unbalanced write workloads. In this work, we propose ECC-Map, a new wear-leveling device architecture that can level even the most unbalanced and adversarial workloads, while enjoying low mapping complexity compared to full indirection. Its key idea is using a family of efficiently computable mapping functions allowing to selectively remap heavily written addresses, while controlling the mapping costs by limiting the number of functions used at any given time. ECC-Map is evaluated on common synthetic workloads, and is shown to significantly outperform existing wear-leveling architectures. The advantage of ECC-Map grows with the device’s size-to-endurance ratio, a parameter that is expected to grow in the scaling trend of growing capacities and shrinking reliabilities.
- Dmytro Apalkov, Alexey Khvalkovskiy, Steven Watts, Vladimir Nikitin, Xueti Tang, Daniel Lottis, Kiseok Moon, Xiao Luo, Eugene Chen, and Adrian Ong. 2013. Spin-transfer torque magnetic random access memory (STT-MRAM). ACM Journal on Emerging Technologies in Computing Systems (JETC) 9, 2 (2013), 1–35.Google ScholarDigital Library
- Paul H. Bardell, William H. McAnney, and Jacob Savir. 1987. Built-in Test for VLSI: Pseudorandom Techniques. Wiley-Interscience.Google Scholar
- Yu-Ming Chang, Pi-Cheng Hsiu, Yuan-Hao Chang, Chi-Hao Chen, Tei-Wei Kuo, and Cheng-Yuan Michael Wang. 2016. Improving PCM Endurance with a Constant-Cost Wear Leveling Design. ACM Trans. Des. Autom. Electron. Syst. 22, 1, Article 9 (jun 2016), 27 pages.Google Scholar
- Chi-Hao Chen, Pi-Cheng Hsiu, Tei-Wei Kuo, Chia-Lin Yang, and Cheng-Yuan Michael Wang. 2012. Age-Based PCM Wear Leveling with Nearly Zero Search Cost. In Proceedings of the 49th Annual Design Automation Conference (San Francisco, California) (DAC ’12). Association for Computing Machinery, New York, NY, USA, 453–458.Google ScholarDigital Library
- Sheng-Wei Cheng, Yuan-Hao Chang, Tseng-Yi Chen, Yu-Fen Chang, Hsin-Wen Wei, and Wei-Kuan Shih. 2016. Efficient Warranty-Aware Wear Leveling for Embedded Systems With PCM Main Memory. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24, 7 (2016), 2535–2547.Google ScholarCross Ref
- Sangyeun Cho and Hyunjin Lee. 2009. Flip-N-Write: A Simple Deterministic Technique to Improve PRAM Write Performance, Energy and Endurance. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (New York, New York) (MICRO 42). Association for Computing Machinery, New York, NY, USA, 347–357.Google ScholarDigital Library
- George C. Clark and J. Bibb. Cain. 1981. Error-correction coding for digital communications. Plenum Press New York.Google Scholar
- Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun, Naehyuck Chang, and Yuan Xie. 2010. Energy-and endurance-aware design of phase change memory caches. In 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010). IEEE, 136–141.Google Scholar
- Miguel Angel Lastras-Montano and Kwang-Ting Cheng. 2018. Resistive random-access memory based on ratioed memristors. Nature Electronics 1, 8 (2018), 466–472.Google ScholarCross Ref
- Benjamin C. Lee, Engin Ipek, Onur Mutlu, and Doug Burger. 2009. Architecting Phase Change Memory as a Scalable Dram Alternative. SIGARCH Comput. Archit. News 37, 3 (jun 2009), 2–13.Google ScholarDigital Library
- Dongzhe Ma, Jianhua Feng, and Guoliang Li. 2014. A Survey of Address Translation Technologies for Flash Memories. ACM Comput. Surv. 46, 3, Article 36 (jan 2014), 39 pages. https://doi.org/10.1145/2512961Google ScholarDigital Library
- Frederic P. Miller, Agnes F. Vandome, and John McBrewster. 2009. Cyclic Redundancy Check: Computation of CRC, Mathematics of CRC, Error Detection and Correction, Cyclic Code, List of Hash Functions, Parity Bit, Information... Cksum, Adler- 32, Fletcher’s Checksum. Alpha Press.Google Scholar
- Ardavan Pedram, Stephen Richardson, Mark Horowitz, Sameh Galal, and Shahar Kvatinsky. 2017. Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era. IEEE Design & Test 34, 2 (2017), 39–50.Google ScholarCross Ref
- Moinuddin K. Qureshi, John Karidis, Michele Franceschini, Vijayalakshmi Srinivasan, Luis Lastras, and Bulent Abali. 2009. Enhancing lifetime and security of PCM-based Main Memory with Start-Gap Wear Leveling. In 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). 14–23.Google ScholarDigital Library
- Andre Seznec. 2010. A Phase Change Memory as a Secure Main Memory. IEEE Computer Architecture Letters 9, 1 (2010), 5–8.Google ScholarDigital Library
- Xin Shi, Fei Wu, Shunzhuo Wang, Changsheng Xie, and Zhonghai Lu. 2018. Program error rate-based wear leveling for NAND flash memory. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 1241–1246.Google Scholar
- Tae-Sun Chung and Dong-Joo Park and Sangwon Park and Dong-Ho Lee and Sang-Won Lee and Ha-Joo Song. 2009. A survey of Flash Translation Layer. Journal of Systems Architecture 55, 5 (2009), 332–343.Google ScholarDigital Library
- Thomas E. Tkacik. 2003. A Hardware Random Number Generator. In Cryptographic Hardware and Embedded Systems - CHES 2002, Burton S. Kaliski, çetin K. Koç, and Christof Paar (Eds.). Springer Berlin Heidelberg, Berlin, Heidelberg, 450–453.Google Scholar
- Debao Wei, Liyan Qiao, Xiaoyu Chen, Mengqi Hao, and Xiyuan Peng. 2019. SREA: A self-recovery effect aware wear-leveling strategy for the reliability extension of NAND flash memory. Microelectronics Reliability 100-101 (2019), 113433. 30th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis.Google Scholar
- H-S Philip Wong, Simone Raoux, SangBum Kim, Jiale Liang, John P Reifenberg, Bipin Rajendran, Mehdi Asheghi, and Kenneth E Goodson. 2010. Phase change memory. Proc. IEEE 98, 12 (2010), 2201–2227.Google ScholarCross Ref
- Ming-Chang Yang, Yu-Ming Chang, Che-Wei Tsao, Po-Chun Huang, Yuan-Hao Chang, and Tei-Wei Kuo. 2014. Garbage collection and wear leveling for flash memory: Past and future. In 2014 International Conference on Smart Computing. 66–73.Google ScholarCross Ref
- Yuan Hua Yang, Xian Bin Xu, Shui Bing He, Fang Zhen, and Yu Ping Zhang. 2013. WLVT: A Static Wear-Leveling Algorithm with Variable Threshold. In Advanced Materials Research, Vol. 756. Trans Tech Publ, 3131–3135.Google Scholar
- Leonid Yavits, Lois Orosa, Suyash Mahar, João Dinis Ferreira, Mattan Erez, Ran Ginosar, and Onur Mutlu. 2020. WoLFRaM: Enhancing Wear-Leveling and Fault Tolerance in Resistive Memories using Programmable Address Decoders. In 2020 IEEE 38th International Conference on Computer Design (ICCD). 187–196.Google ScholarCross Ref
- HanBin Yoon, Justin Meza, Rachata Ausavarungnirun, Rachael A. Harding, and Onur Mutlu. 2012. Row buffer locality aware caching policies for hybrid memories. In 2012 IEEE 30th International Conference on Computer Design (ICCD). 337–344.Google ScholarDigital Library
- Wangyuan Zhang and Tao Li. 2009. Characterizing and mitigating the impact of process variations on phase change based memory systems. In 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). 2–13.Google ScholarDigital Library
- Ping Zhou, Bo Zhao, Jun Yang, and Youtao Zhang. 2009. A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology. SIGARCH Comput. Archit. News 37, 3 (jun 2009), 14–23.Google ScholarDigital Library
- Wen Zhou, Dan Feng, Yu Hua, Jingning Liu, Fangting Huang, and Pengfei Zuo. 2016. Increasing lifetime and security of phase-change memory with endurance variation. In 2016 IEEE 22nd International conference on parallel and distributed systems (ICPADS). IEEE, 861–868.Google ScholarCross Ref
Index Terms
- ECC-Map: A Resilient Wear-Leveled Memory-Device Architecture with Low Mapping Overhead
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