Frank Schirrmeister
ABSTRACT
Modern System-on-Chip (SoC) architectures and chiplet-based designs often re-use and connect 100’s computing and interface blocks, some of which will share caches and external memories in a cache-coherent fashion. Network-on-chip (NoC) implementations can take up 10 to 12 % of chip area, significantly impacting performance, power consumption, and cost [1]. DRAM performance plays a significant role in system performance, and its impact needs to be understood as early as possible during a design flow.
This presentation will discuss different protocol options for RISC-V-based SoCs in the context of their unique advantages in terms of flexibility, performance, and coherency. We introduce NoC development frameworks for cache-coherent applications like AMBA CHI and ACE [2] and non-coherent applications, enabling better architecture optimization and management of physical constraints and reducing interconnect area and power consumption. We will compare critical aspects of the different NoC protocols AMBA 3 AXI, AMBA 4 AXI and ACE, AMBA 5 CHI, and TileLink and discuss the impact of chiplet-based design on NoC protocols. We will also discuss the challenges caused by floor planning and physical layout on NoC topology development with approaches that can achieve up to 5X shorter turn-around time than manual iterations.
Using concrete examples, we will discuss the effect of DRAMs on the system and NoC performance, and we will discuss integration challenges and solutions between development frameworks like Arteris FlexNoc™1 and NCore™2 with Synopsys Platform Architect3 and Fraunhofer DRAMSys [4].
Supplemental Material
Available for Download
Extended Abstract for "Addressing DRAM Performance Analysis Challenges for Network-on-Chip (NoC) Design"
Extended Abstract for "Addressing DRAM Performance Analysis Challenges for Network-on-Chip (NoC) Design"
Extended abstract for ?Addressing DRAM Performance Analysis Challenges for Network-on-Chip (NoC) Design?
- G. De Micheli, C. Seiculescu, S. Murali, L. Benini, F. Angiolini, and A. Pullini. 2010. Networks on Chips: From Research to Products. In Proceedings of the 47th Design Automation Conference (Anaheim, California) (DAC ’10). Association for Computing Machinery, New York, NY, USA, 300–305. https://doi.org/10.1145/1837274.1837352Google Scholar
Digital Library
- Michael Frank. 2020. A Flexible Multiprotocol Cache Coherent Network-on-Chip (NoC) for Heterogeneous SoCs. In Linley Fall Conference.Google Scholar
- A.B. Kahng, J. Lienig, I.L. Markov, and J. Hu. 2011. VLSI Physical Design: From Graph Partitioning to Timing Closure. Springer Netherlands.Google Scholar
- Lukas Steiner, Matthias Jung, Felipe S. Prado, Kirill Bykov, and Norbert Wehn. 2022. DRAMSys4.0: An Open-Source Simulation Framework for In-depth DRAM Analyses. International Journal of Parallel Programming 50, 2 (01 Apr 2022), 217–242. https://doi.org/10.1007/s10766-022-00727-4Google ScholarDigital Library
Index Terms
- Addressing DRAM Performance Analysis Challenges for Network-on-Chip (NoC) Design
Recommendations
On-Chip Operating System Design for NoC-Based CMP
CIT '10: Proceedings of the 2010 10th IEEE International Conference on Computer and Information TechnologyNetworks on Chip (NoCs) are considered to be the best candidate for the future on-chip communication of Chip Multiprocessors (CMPs). However, till date, general-purpose operating systems (OSs) for NoC-based CMP have not been examined. As the trend of ...
An energy-efficient design of microkernel-based on-chip OS for NOC-based manycore system
The chip multiprocessor is the most prolific processor design because its many cores enhance system performance. Network on chip (NOC) has been proposed as a promising model to solve the connection problem of the cores. However, a new challenge consists ...
A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip
ISVLSI '09: Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSINetworks-on-chip (NoCs) can improve the communication bandwidth and power efficiency of multiprocessor systems-on-chip (MPSoC). However, traditional metallic interconnects consume significant amount of power to deliver even higher communication ...
Comments