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Design of High-speed CMOS Image Sensor Data Acquisition Based on FPGA

Published: 28 February 2024 Publication History

Abstract

In recent years, LVDS transmission has been widely used in high-speed information transmission [1], and FPGA is used as a receiver chip for LVDS signals in high-speed data transmission examples. Compared with the traditional LVDS data interaction based on SRIO [2], AROURA [3] and other protocols, this paper designs a data processing scheme for high-speed CMOS under the FPGA platform, high-speed CMOS data output without coding, multi-channel (from tens to hundreds of channels) parallel transmission form, so that the timing control and data restoration of the acquisition end is more difficult, this design through the multi-channel LVDS data bit reception, parallel processing and channel synchronization work. The design of the whole set of data acquisition scheme is completed, and the method is verified by experiments, which realizes the reception, parallel processing and channel synchronization of LVDS data in each channel, ensuring the stability and reliability of data during transmission.

References

[1]
LIU Yuecheng. Design of high-resolution image acquisition device based on FPGA [D]. North central university, 2023. /, dc nki. GHBGC. 2023.001371.
[2]
XUE Pei, GUAN Jian, SHAO Chunwei, Design and implementation of SRIO multi-channel control system based on FPGA[J].Electronic Technology Application,2023,49(01):107-113.
[3]
LI Yun,YUAN Xingmeng,XU Lantian. Research on high-speed transmission system and FPGA implementation of Aurora protocol[J].Electronic Products World,2023,30(06):54-58.)
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Xie Tianyuan. Research and design of high-speed CMOS_SubLVDS Transceiver circuit [D]. Xian university of electronic science and technology, 2023. /, dc nki. Gxadu. 2022.002554.
[5]
Huo Hailong, Zhang Guangyuan, Zeng Xiangzhong. A design of LVDS data string parallel conversion based on FPGA [J]. Yangtze River Information and Communication,2023,36(04):113-117. (in Chinese)
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Yang Shutian. Design and implementation of multi-channel data harvester based on FPGA [D]. North central university, 2023. /, dc nki. GHBGC. 2022.000291.
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Sun Yukai, Ma Xun, Wang Yao Design of high-speed CMOS LVDS Transceiver Circuit [J]. China Integrated Circuits,2022,31(05):47-50. (in Chinese)
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Jiang Hongyang. High-speed LVDS signal reception and series parallel conversion based on FPGA Electronic Technology and Software Engineering,2016(23):99-100.
[9]
Wang Zheng, Zhang Bin. A method of LVDS data Receiving based on FPGA [J] Chinese Journal of Technology and Applications, 2019,37 (07): 115-116. (in Chinese) j.Czynki.Cn12-1369.2019.07.61.
[10]
Zhang C. Research and implementation of data sending and receiving system based on LVDS [D]. Xi 'an Diandian Corporation Zi University of Science and Technology,2017.

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  1. Design of High-speed CMOS Image Sensor Data Acquisition Based on FPGA

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    ICCPR '23: Proceedings of the 2023 12th International Conference on Computing and Pattern Recognition
    October 2023
    589 pages
    ISBN:9798400707988
    DOI:10.1145/3633637
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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    Association for Computing Machinery

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    Publication History

    Published: 28 February 2024

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    Author Tags

    1. FPGA
    2. LVDS
    3. data acquisition,high speed,CMOS
    4. multi-channel

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