Junyu Jiang
ABSTRACT
In recent years, with the continuous progress of integrated circuit technology, the performance requirements of digital circuit adder are getting higher and higher. The size and voltage of gate capacitance have important effects on the performance of the adder, especially the delay and power consumption. To solve this problem, an optimization strategy is proposed through transistor size optimization to improve the performance of the adder. This study investigates the impact of gate capacitance size and voltage on adder performance, specifically in terms of delay and power consumption. Optimization strategies are proposed through transistor size optimization. The paper introduces adder principles and design methods, analyzing adder delay and power consumption characteristics under different gate capacitance sizes. Transistor size optimization is performed to validate the proposed strategies. The research contributes to adder design and optimization by providing insights into the influence patterns of gate capacitance size. It identifies an optimal design solution that balances delay and power consumption, enhancing the overall performance and efficiency of computing systems.
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