ABSTRACT
With the exponential growth of Very Large-Scale Integration (VLSI) scale and complexity, traditional algorithms of Electronic Design Automation (EDA) are gradually encountering bottlenecks. The successful application of Machine Learning (ML) in various fields has opened a new path for the development of EDA. The ML model has strong adaptability and generalization ability, which can discover patterns in complex circuit designs, make fast and accurate predictions, and effectively optimize with high quality. Data serves as an important link between ML algorithms and circuit design, and effective data features can improve the assistance of ML models to EDA. This article provides a summary of the front-end of circuit design and selects an ML based EDA application framework with typical data characteristics. It analyzes the data and features in each ML model, lists their predictions or optimizations based on algorithms, and proposes suggestions and considerations for the future development trend of this field. Academic research has demonstrated the enormous potential of ML in EDA applications. Future development requires the integration of stakeholders in the entire design and EDA ecosystem to bring future expansion benefits to the entire industry and society.
- Rapp M. 2022. MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper. IEEE Transactions on Computer-Aided Design of Integrated Circuits and System 41, 10 (October 2022), 3162-3181. https://doi.org/10.1109/TCAD.2021.3124762Google ScholarDigital Library
- Kahng A B. 2023. Machine Learning for CAD/EDA: The Road Ahead. J. IEEE Design & Test, 40, 1 (Feb. 2023), 8-16. https://doi.org/10.1109/MDAT.2022.3161593Google ScholarCross Ref
- Deng J, Dong W, Socher R,et al. 2019. ImageNet: A large-scale hierarchical image database. 2009 IEEE Conference on Computer Vision and Pattern Recognition. Miami, FL, USA, 248-255. https://doi.org/10.1109/CVPR.2009.5206848Google ScholarCross Ref
- Kononenko I, Kukar M. 2000. Machine Learning and Data Mining. J. Journal of Shijiazhuang Vocational Technology Institute, 2000, 110-114. https://doi.org/10.1145/380995.381059Google ScholarDigital Library
- Feng W, Ma C, Zhao G and Zhang R. FSRF:An Improved Random Forest for Classification. 2020 IEEE International Conference on Advances in Electrical Engineering and Computer Applications (AEECA). Dalian, China, 173-178. https://doi.org/10.1109/AEECA49918.2020.9213456Google ScholarCross Ref
- Elfadel I A M, Boning D S, Li X. 2019. Machine Learning in VLSI Computer-Aided Design.Google Scholar
- Chen T, Chen X, Chen W, 2021. Learning to Optimize: A Primer and A Benchmark. In ArXiv. https://doi.org/10.48550/arXiv.2103.12828Google ScholarCross Ref
- Roy, R, Godil, S. 2022. Machine Learning for Logic Synthesis. In Machine Learning Applications in Electronic Design Automation. Springer. https://doi.org/10.1007/978-3-031-13074-8_7Google ScholarCross Ref
- Alrahis L, Knechtel J and Sinanoglu O. 2023. Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs. 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, 83-90.Google Scholar
- Ustun E, Deng C, Pal D, Li Z and Zhang Z. 2020. Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks. 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD). IEEE, San Diego, CA, USA, 1-9.Google Scholar
- Zennaro E, Servadei L, Devarajegowda K and Ecker W. 2018. A Machine Learning Approach for Area Prediction of Hardware Designs from Abstract Specifications. 2018 21st Euromicro Conference on Digital System Design (DSD). Prague, Czech Republic, 413-420. https://doi.org/10.1109/DSD.2018.00076Google ScholarCross Ref
- Chen H and Shen M. 2019. A Deep-Reinforcement-Learning-Based Scheduler for FPGA HLS. 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). Westminster, CO, USA, 1-8. https://doi.org/10.1109/ICCAD45719.2019.8942126Google ScholarCross Ref
- Zhang Y, Ren H and Khailany B. 2020. GRANNITE: Graph Neural Network Inference for Transferable Power Estimation. 2020 57th ACM/IEEE Design Automation Conference (DAC). San Francisco, CA, USA, 16. https://doi.org/10.1109/DAC18072.2020.9218643Google ScholarCross Ref
- Pasandi G, Peterson M, Herrera M. 2020. Deep-PowerX: A Deep Learning-Based Framework for Low-Power Approximate Logic Synthesis. J. ACM, (August 2020), 73-78. https://doi.org/10.1145/3370748.3406555Google ScholarDigital Library
- Hosny A, Hashemi S, Shalan M. 2020. DRiLLS: Deep Reinforcement Learning for Logic Synthesis. 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC). Beijing, China, 581-586, https://doi.org/10.1109/ASP-DAC47756.2020.9045559Google ScholarDigital Library
- Xie Z, Huang Y H, Fang G Q. 2018. RouteNet: Routability Prediction for Mixed-Size Designs Using Convolutional Neural Network. 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). San Diego, CA, USA, 1-8, https://doi.org/10.1145/3240765.3240843Google ScholarDigital Library
- Lin Y, Jiang Z, Gu J. 2021. DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement. J. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 40, 4 (April 2021), 748-761, https://doi.org/10.1109/TCAD.2020.3003843Google ScholarCross Ref
- Liang R, Nath S, Rajaram A, Hu J and Ren H, 2023. BufFormer: A Generative ML Framework for Scalable Buffering. 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC). Tokyo, Japan, 264-270.Google ScholarDigital Library
- Yu C, Zhang Z. 2019. Painting on Placement: Forecasting Routing Congestion using Conditional Generative Adversarial Nets. 2019 56th ACM/IEEE Design Automation Conference (DAC). Las Vegas, NV, USA, 1-6.Google ScholarDigital Library
- Zhang X, Wang J, Zhu C. 2019. DNNBuilder: an Automated Tool for Building High-Performance DNN Hardware Accelerators for FPGAs. 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). San Diego, CA, USA, 1-8. https://doi.org/10.1145/3240765.3240801Google ScholarDigital Library
- Blocklove, J., Garg, S., Karri, R., & Pearce, H.A. 2023. Chip-Chat: Challenges and Opportunities in Conversational Hardware Design. In ArXiv. https://doi.org/10.48550/arXiv.2305.13243Google ScholarCross Ref
Recommendations
Embracing Machine Learning in EDA
ISPD '22: Proceedings of the 2022 International Symposium on Physical DesignThe application of machine learning (ML) in EDA is a hot research trend. To use ML in EDA, it is nature to think from the ML method point of view, i.e. supervised learning, reinforcement learning and unsupervised learning. Based on this point of view, ...
Machine Learning for Electronic Design Automation: A Survey
With the down-scaling of CMOS technology, the design complexity of very large-scale integrated is increasing. Although the application of machine learning (ML) techniques in electronic design automation (EDA) can trace its history back to the 1990s, the ...
Machine Learning: The State of the Art
The two fundamental problems in machine learning (ML) are statistical analysis and algorithm design. The former tells us the principles of the mathematical models that we establish from the observation data. The latter defines the conditions on which ...
Comments