Xianming Liu
ABSTRACT
The machine learning approach improves design efficiency and reduces design time by simulating automated sizing and placement of integrated circuits ( ICs), but the complexity of solving a strict constraint is not neglected. This paper proposed an automation analog IC parameter design framework based on Bayesian optimization (BO). The BO searches the global optimal design variables, which benefits dealing with multiple constraints optimization problems. To guarantees all the transistor works in normal conditions, the constraint test is introduced during the sampling procedure. At the local search phase, the Gaussian processes (GP) surrogate-based model predicts the circuit's performance instead of SPICE simulation. The BO combined GP approach is friendly to finding the optimal design. The proposed algorithm can handle multi-objective optimization problems. The experiments use a two-stage operational amplifier (Op-amp) and biased-based folded cascode CMOS operational amplifier to test the performance of the algorithm. The experiment results show that the proposed method can speed up the optimization process and perform better than the state-of-the-art surrogate-based optimization method.
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