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PONO: Power Optimization with Near Optimal SMT-based Sub-circuit Generation

Published: 07 November 2024 Publication History

Abstract

Generating high-quality sub-circuits for local substitution is an effective optimization technique in logic synthesis. There have been abundant works on generating area- and delay-optimal sub-circuits, greatly enhancing the logic optimization quality. However, power-oriented sub-circuit generation is rarely discussed, while optimizing power consumption in this sub-15 nm era is of paramount interest. We propose PONO, an SMT-based near optimal sub-circuit generation flow for power optimization. PONO enables power-oriented circuit library building and fills the gap in generating circuits near the Pareto frontier in PPA (Power, Performance, and Area). It manifests superiority in power reduction over traditional one in rewrite, a key logic optimization algorithm. We test PONO on EFPL benchmarks, and it shows 8.7% less power consumption without degrading the post-place-and-route performance and area.

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cover image ACM Conferences
DAC '24: Proceedings of the 61st ACM/IEEE Design Automation Conference
June 2024
2159 pages
ISBN:9798400706011
DOI:10.1145/3649329
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Publication History

Published: 07 November 2024

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Author Tags

  1. logic synthesis
  2. SMT problem
  3. synthesis for low power

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DAC '24
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DAC '24: 61st ACM/IEEE Design Automation Conference
June 23 - 27, 2024
CA, San Francisco, USA

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