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A Combined Content Addressable Memory and In-Memory Processing Approach for k-Clique Counting Acceleration

Published: 07 November 2024 Publication History

Abstract

k-Clique counting problem plays an important role in graph mining which has seen a growing number of applications. However, current k-Clique counting accelerators cannot meet the performance requirement mainly because they struggle with high data transfer issue incurred by the intensive set intersection operations and the inability of load balancing. In this paper, we propose to solve this problem with a hybrid framework of content addressable memory (CAM) and in-memory processing (PIM). Specifically, we first utilize CAM for binary induced subgraph generation in order to reduce the search space, then we use PIM to implement in-place parallel k-Clique counting through iterative Boolean logic "AND" like operation. To take full advantage of this combined CAM and PIM framework, we develop dynamic task scheduling strategies that can achieve near optimal load balancing among the PIM arrays. Experimental results demonstrate that, compared with state-of-the-art CPU and GPU platforms, our approach achieves speedups of 167.5× and 28.8×, respectively. Meanwhile, the energy efficiency is improved by 788.3× over the GPU baseline.

References

[1]
Yixiang Fang, Kaiqiang Yu, Reynold Cheng, Laks VS Lakshmanan, and Xuemin Lin. Efficient algorithms for densest subgraph discovery. Proceedings of the VLDB Endowment, 12(11):1719--1732, 2019.
[2]
Balázs Adamcsek, Gergely Palla, Illés J Farkas, Imre Derényi, and Tamás Vicsek. Cfinder: locating cliques and overlapping modules in biological networks. Bioinformatics, 22(8):1021--1023, 2006.
[3]
Dr Samuel Manoharan and Ammayappan Sathesh. Patient diet recommendation system using k clique and deep learning classifiers. Journal of Artificial Intelligence and Capsule Networks, 2(2):121--130, 2020.
[4]
Jessica Shi, Laxman Dhulipala, and Julian Shun. Parallel clique counting and peeling algorithms. In SIAM Conference on Applied and Computational Discrete Algorithms (ACDA21), pages 135--146. SIAM, 2021.
[5]
Shweta Jain and C Seshadhri. The power of pivoting for exact clique counting. In Proceedings of the 13th International Conference on Web Search and Data Mining, pages 268--276, 2020.
[6]
Mohammad Almasri, Izzat El Hajj, Rakesh Nagi, Jinjun Xiong, and Wen-mei Hwu. Parallel k-clique counting on gpus. In Proceedings of the 36th ACM International Conference on Supercomputing, pages 1--14, 2022.
[7]
Guohao Dai, Zhenhua Zhu, Tianyu Fu, Chiyue Wei, Bangyan Wang, Xiangyu Li, Yuan Xie, Huazhong Yang, and Yu Wang. Dimmining: pruning-efficient and parallel graph mining on near-memory-computing. In Proceedings of the 49th Annual International Symposium on Computer Architecture, pages 130--145, 2022.
[8]
Yuntao Wei, Xueyan Wang, Shangtong Zhang, Jianlei Yang, Xiaotao Jia, Zhaohao Wang, Gang Qu, and Weisheng Zhao. Imga: Efficient in-memory graph convolution network aggregation with data flow optimizations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023.
[9]
Xuhang Chen, Xueyan Wang, Xiaotao Jia, Jianlei Yang, Gang Qu, and Weisheng Zhao. Accelerating graph-connected component computation with emerging processing-in-memory architecture. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(12):5333--5342, 2022.
[10]
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, and Weisheng Zhao. Tcim: triangle counting acceleration with processing-in-mram architecture. In 2020 57th ACM/IEEE Design Automation Conference (DAC), pages 1--6. IEEE, 2020.
[11]
Tianyu Fu, Chiyue Wei, Zhenhua Zhu, Shang Yang, Zhongming Yu, Guohao Dai, Huazhong Yang, and Yu Wang. Clap: Locality aware and parallel triangle counting with content addressable memory. In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), pages 1--6. IEEE, 2023.
[12]
Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, and Weisheng Zhao. Nand-spin-based processing-in-mram architecture for convolutional neural network acceleration. Science China Information Sciences, 66(4):142401, 2023.
[13]
Didi Zhang, Bi Wu, Haonan Zhu, and Weiqiang Liu. Capacity-oriented highperformance nv-tcam leveraging hybrid mram scheme. In Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, pages 1--6, 2022.
[14]
Hao Cai, You Wang, Lirida Alves De Barros Naviner, and Weisheng Zhao. Robust ultra-low power non-volatile logic-in-memory circuits in fd-soi technology. IEEE Transactions on Circuits and Systems I: Regular Papers, 64(4):847--857, 2016.
[15]
Jure Leskovec and Andrej Krevl. SNAP Datasets: Stanford large network dataset collection. http://snap.stanford.edu/data, June 2014.

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cover image ACM Conferences
DAC '24: Proceedings of the 61st ACM/IEEE Design Automation Conference
June 2024
2159 pages
ISBN:9798400706011
DOI:10.1145/3649329
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Published: 07 November 2024

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Author Tags

  1. k-clique counting
  2. processing-in-memory
  3. content addressable memory
  4. hybrid framework

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DAC '24
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DAC '24: 61st ACM/IEEE Design Automation Conference
June 23 - 27, 2024
CA, San Francisco, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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