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Improving the Efficiency of In-Memory-Computing Macro with a Hybrid Analog-Digital Computing Mode for Lossless Neural Network Inference

Published: 07 November 2024 Publication History

Abstract

Analog in-memory-computing (IMC) is an attractive technique with a higher energy efficiency to process machine learning workloads. However, the analog computing scheme suffers from large interface circuit overhead. In this work, we propose a macro with a hybrid analog-digital mode computation to reduce the precision requirement of the interface circuit. Considering the distribution of the multiplication and accumulation (MAC) value, we propose a nonlinear transfer function of the computing circuits by only accurately computing low MAC value in the analog domain with a digital mode to deal with the high MAC value with smaller possibility. Silicon measurement results show that the proposed macro could achieve 160 GOPS/mm2 area efficiency and 25.5 TOPS/W for 8b/8b matrix computation. The architectural-level evaluation for real workloads shows that the proposed macro can achieve up to 2.92× higher energy efficiency than conventional analog IMC designs.

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              cover image ACM Conferences
              DAC '24: Proceedings of the 61st ACM/IEEE Design Automation Conference
              June 2024
              2159 pages
              ISBN:9798400706011
              DOI:10.1145/3649329
              This work is licensed under a Creative Commons Attribution International 4.0 License.

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              Published: 07 November 2024

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              Author Tags

              1. processing-in-memory
              2. SRAM
              3. machine learning acceleration

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              DAC '24: 61st ACM/IEEE Design Automation Conference
              June 23 - 27, 2024
              CA, San Francisco, USA

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              Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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