skip to main content
10.1145/3649476.3658788acmconferencesArticle/Chapter ViewAbstractPublication PagesglsvlsiConference Proceedingsconference-collections
short-paper
Open access

An Automatic Insertion Scheme of Extra Via for DSA-MP Hybrid Lithography

Published: 12 June 2024 Publication History

Abstract

With the continuous shrinking of feature size, directed self-assembly (DSA) has gradually become one of the leading candidates for extending the resolution of optical lithography to sub-7 nm and beyond, a DSA-based extra via (EV) insertion scheme is the key to guarantee the reliability of integrated circuit when applying DSA during manufacturing. In this paper, we proposed an automatic insertion algorithm of extra via taking the manufacturing cost of the guiding template in DSA into consideration in the EV insertion process, which makes the total cost of subsequent DSA-MP hybrid lithography controllable, while maintaining a high insertion rate of EV. The simulation results show that, with the same experimental patterns, the insertion rate of EVs is increased by about 10% compared with the previous integer linear programming method.

References

[1]
Mark Neisser. 2021. International Roadmap for Devices and Systems lithography roadmap. Journal of Micro/Nanopatterning Materials and Metrology, vol. 20, no. 4, pp. 044601, 2021.
[2]
Zhiyong Wu 2023. Contact Hole Multiplication by Directed Self-Assembly of Block Copolymer with Homopolymer-Blending. In IWAPS, 1-4.
[3]
Kenji Yoshimoto and Takashi Taniguchi. 2013. Large-scale dynamics of directed self-assembly defects on chemically pre-patterned surface. Alternative Lithographic Technologies V.
[4]
Yuansheng Ma 2015. Directed self-assembly graphoepitaxy template generation with immersion lithography. Journal of Micro/Nanolithography, MEMS, and MOEMS, vol. 14.
[5]
Yuansheng Ma 2017. Design technology co-optimization (DTCO) study on self-aligned-via (SAV) with Lamella DSA for sub-7 nm technology. Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480B (30 March 2017).
[6]
Kun-Lin Lin, Shao-Yun Fang and Yun-Xiang Hong. 2017. Design optimization considering guiding template feasibility and redundant via insertion for directed self-assembly. IEEE Transactions on Circuits and Systems I: Regular Papers, 2017, 63(12): 3172-3182
[7]
Xingquan Li 2018. Graph-based redundant via insertion and guiding template assignment for DSA-MP. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018, 26(11): 2504-2517
[8]
Tao Zhang, Hengyu Zhou, Sikun Li, Shisheng Xiong and Xiangzhao Wang. 2022. A Generation solving Layout Decomposition Method for DSA-MP Hybrid Lithography. In IWAPS, 1-4.
[9]
He Yi 2012. Contact-hole patterning for random logic circuits using block copolymer directed self-assembly. Proc. SPIE 8323, Alternative Lithographic Technologies IV, 83230W (21 March 2012).
[10]
He Yi, Xin-Yu Bao, Richard Tiberio and H.-S. Philip Wong. 2015. A general design strategy for block copolymer directed self-assembly patterning of integrated circuits contact holes using an alphabet approach. Nano Lett. 2015 Feb 11;15(2):805-12.
[11]
Xingquan Li 2019. A local optimal method on DSA guiding template assignment with redundant/dummy via insertion. In ASPDAC '19, 305-10.
[12]
Daifeng Guo, Maryann Tung, Ioannis Karageorgos, H.-S. Philip Wong and Martin D. F. Wong. 2017. Density driven placement of sub-DSA resolution assistant features (SDRAFs). Proc. SPIE 10148, Design-Process-Technology Co-optimization for Manufacturability XI, 101480E (28 March 2017).
[13]
Ioannis Karageorgos 2016. Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits. J. Micro/Nanolith. MEMS MOEMS 15(4) 043506 (7 November 2016).
[14]
Jiaojiao Ou, Bei Yu, and David Z. Pan. 2016. Concurrent Guiding Template Assignment and Redundant via Insertion for DSA-MP Hybrid Lithography. In ISPD '16, 39–46.
[15]
Yun -Jhe Jiang, Kuo -Hao Wu and Shao -Yun Fang. 2021. Manufacturability Enhancement With Dummy via Insertion for DSA-MP Lithography Using Multiple BCP Materials. In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 2, pp. 400-404.

Index Terms

  1. An Automatic Insertion Scheme of Extra Via for DSA-MP Hybrid Lithography

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Conferences
    GLSVLSI '24: Proceedings of the Great Lakes Symposium on VLSI 2024
    June 2024
    797 pages
    ISBN:9798400706059
    DOI:10.1145/3649476
    This work is licensed under a Creative Commons Attribution International 4.0 License.

    Sponsors

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Publication History

    Published: 12 June 2024

    Check for updates

    Author Tags

    1. Directed self-assembly (DSA)
    2. Dummy vias
    3. Guiding template
    4. Redundant vias

    Qualifiers

    • Short-paper
    • Research
    • Refereed limited

    Funding Sources

    Conference

    GLSVLSI '24
    Sponsor:
    GLSVLSI '24: Great Lakes Symposium on VLSI 2024
    June 12 - 14, 2024
    FL, Clearwater, USA

    Acceptance Rates

    Overall Acceptance Rate 312 of 1,156 submissions, 27%

    Upcoming Conference

    GLSVLSI '25
    Great Lakes Symposium on VLSI 2025
    June 30 - July 2, 2025
    New Orleans , LA , USA

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • 0
      Total Citations
    • 165
      Total Downloads
    • Downloads (Last 12 months)165
    • Downloads (Last 6 weeks)38
    Reflects downloads up to 18 Jan 2025

    Other Metrics

    Citations

    View Options

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    HTML Format

    View this article in HTML Format.

    HTML Format

    Login options

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media